Leakage power reduction techniques of 45 nm static random access memory (SRAM) cells (original) (raw)
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Study of Speed and Leakage Power Trade-off in Various SRAM Circuits for Mobile Application
International Journal on Emerging Technologies (Special Issue NCETST-2017), 2017
The growing demand of multimedia rich applications in handled portable mobile devices continuously driving the need for bigger and higher speed embedded Static Random Access Memory (SRAM) to boost the system performance. Lots of circuit technique, e.g. body bias, bit charge recycle etc., have been proposed to expand design margins at low voltage operation while reducing leakage current at standby condition, but the performance is analyze at the rate of speed and this issue is not addressed widely. Also due to unbroken scaling of CMOS, the process variation also affect the feature of SRAMs. Paper presents the study of low leakage SRAM along with the speed factor.
Comparative analysis of SRAM cell with leakage power reduction approaches
International Journal of Engineering & Technology, 2018
In deep sub-micron technologies, high number of transistors is mounted onto a small chip area where, SRAM plays a vital role and is considered as a major part in many VLSI ICs because of its large density of storage and very less access time. Due to the demand of low power applications the design of low power and low voltage memory is a demanding task. In these memories majority of power dissipation depends on leakage power. This paper analyzes the basic 6T SRAM cell operation. Here two different leakage power reduction approaches are introduced to apply for basic 6T SRAM. The performance analysis of basic SRAM cell, SRAM cell using drowsy-cache approach and SRAM cell using clamping diode are designed at 130nm using Mentor Graphics IC Studio tool. The proposed SRAM cell using clamping diode proves to be a better power reduction technique in terms of power as compared with others SRAM structures. At 3.3V, power saving by the proposed SRAM cell is 20% less than associated to basic 6T ...
Speed and Leakage Power Trade-off in Various SRAM Circuits
International Journal of …, 2011
The growing demand of multimedia rich applications in handled portable devices continuously driving the need for large and high speed embedded Static Random Access Memory (SRAM) to enhance the system performance. Many circuit techniques, e.g. body bias, bit charge recycling etc., have been proposed to expand design margins at low voltage operation while reducing leakage current at standby mode, but the performance is analyzed at the cost of speed and this issue is not addressed widely. Also due to continuous scaling of CMOS, the process variations also affect the performance of SRAMs. This paper presents the analysis of low leakage SRAM along with the speed factor.
Subthreshold leakage current reduction techniques for static random access memory
Smart Structures, Devices, and Systems II, 2005
The two main sources of power dissipation in CMOS circuits are dynamic and static power dissipation. Static power dissipation is due to leakage current when the transistor is normally off. The improvement in technology scaling has introduced very large subthreshold leakage current, therefore careful design techniques are very important in order to reduce subthreshold leakage current for low power design. Leakage current occurs in both active and standby modes. It is recommended to switch off the leakage current when the circuit is in standby mode, however it is not always possible to shut off the leakage current completely during this mode. Unlike gate leakage, subthreshold leakage cannot be solved by MOS structures nor by introducing new material. One of the feasible solutions is by combinational use of Low-V t transistors for its high-speed capability and High-V t transistors for very small leakage current. Multi-Threshold CMOS (MTCMOS) and Variable-Threshold CMOS (VTCMOS) are biasing techniques that uses combinations of different threshold voltage and are suitable for SRAM design. Ideally the larger the threshold level the lower the leakage current, however, one must decide the optimum value of threshold level between the power switch (High-V t devices) and (Low-V t devices), as recovery delay tends to increase in higher threshold level. The full paper will discuss the design and performance of SRAM implemented using MTCMOS and VTCMOS biasing techniques. An improved sensing amplifier in the memory cell was incorporated to enhance the circuit performance.
Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell
International journal of physical sciences
In sub-100 nm generation, gate-tunneling leakage current increases and dominates the total standby leakage current of LSIs based on decreasing gate-oxide thickness. Showing that the gate leakage current is effectively reduced by lowering the gate voltage, we propose a local DC level control (LDLC) for static random access memory (SRAM) cell arrays and an automatic gate leakage suppression driver (AGLSD) for peripheral circuits. We designed and analyzed a 32 kb 1-port SRAM using 45 nm CMOS technology. The six-transistor SRAM cell size is 1.25 µm 2 . Evaluation shows that the standby current of 32 kb SRAM is 1.2 µA at 1.2 V and room temperature. It was reduced to 7.5% of the conventional SRAM.
LEAKAGE POWER REDUCTION IN DEEP SUB MICRON SRAM DESIGN -A REVIEW
Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.
Different leakage power reduction techniques in SRAM Circuits: A State-of-the-art Review
2017
1Scholar of M. Tech. in ECE (VLSI Design), Deenbandhu Chhotu Ram University of Science & Technology, Sonepat, India 2,3 A.P., ECED, Deenbandhu Chhotu Ram University of Science & Technology, Sonepat, India --------------------------------------------------------------------------***------------------------------------------------------------------------Abstract In today’s electronic devices, memory is a most important part that shares a major part of total circuit power. With the newer technology size of processing data is increasing which results in increase of memory and overall circuit size. The stored data is affected by the leakage power. There is a major power loss due to the leakage current. The leakage power loss is inversely proportional to size of the circuit which is undesired. The different leakage power reduction technique has been developed to overcome this problem. This paper presents the study of various leakage current in CMOS devices and the reduction techniques use...
SRAM Leakage Suppression by Minimizing Standby Supply Voltage
2004
Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (V DD ) to its limit, which is the Data Retention Voltage (DRV), leakage power can be substantially reduced. This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as process variations, chip temperature, and transistor sizing. An analytical model for DRV as a function of process and design parameters is presented, and forms the base for further design space explorations. This model is verified using simulations as well as measurements from a 4KB SRAM chip in a 0.13µm technology. It is demonstrated that an SRAM cell state can be preserved at sub-300mV standby V DD , with more than 90% leakage power savings.
Trade-off for Leakage Power Reduction in Deep Sub Micron SRAM Design
IJEER, 2016
Present day electronic industry faces the major problem of standby leakage current, as the processor speed increases, there is requirement of high speed cache memory. SRAM being mainly used for cache memory design, several low power techniques are being used for SRAM cell design. Full CMOS 6T SRAM cell is the most preferred choice for digital circuits. This paper reviews various leakage power techniques used in 6T SRAM cell and their comparative study.
Design and Analysis of Two Low-Power SRAM Cell Structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
In this paper, two Static Random Access Memory (SRAM) cells that reduce the static power dissipation due to gate and sub-threshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation.