Design and analysis of 45 nm low power 32 kb embedded static random access memory (SRAM) cell (original) (raw)
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Leakage power reduction techniques of 45 nm static random access memory (SRAM) cells
As the technology scales down to 90 nm and below, static random access memory (SRAM) standby leakage power is becoming one of the most critical concerns for low power applications. In this article, we review three major leakage current components of SRAM cells and also discuss some of the leakage current reduction techniques including body biasing, source biasing, dynamic V DD , negative word line, and bit line floating schemes. All of them are achieved by controlling different terminal voltages of the SRAM cell in standby mode. On the other hand, performance loss occurs simultaneously with leakage saving. To validate the effectiveness of low power techniques, the leakage current, static noise margin, and read current of SRAM cells, based on the UMC 45 nm complementary metal-oxide-semiconductor (CMOS) process with leakage current reduction techniques has been simulated. The results indicate that by using the dynamic V DD and source biasing schemes, greater leakage suppressing capability, although with a higher performance loss, can be obtained. Therefore, the SRAM cell optimization scheme must consider the trade-off between power consumption and speed performance.
STUDY OF LOW-POWER SRAM CELL AT DEEP SUB-MICRON CMOS TECHNOLOGY FOR MOBILE APPLICATIONS
INTERNATIONAL JOURNAL OF RESEARCH IN TECHNOLOGY AND MANAGEMENT (IJRTM), 2017
Life is filled by various modern electronic products. Semiconductor memories are essential parts of these products and have been growing in density & performance in unity with Moore's law like all silicon technology. The process technology has been scaling down from last two decades and to get the functional and high yielding design beyond 100-nm feature sizes the existing design approach needs to be modified to deal with the increased process variation interconnects processing difficulties, and other newly physical effects. Considerable increase in gate direct tunneling current in the nano-CMOS rule is scale of gate oxide. Sub-threshold leakage and gate direct-tunneling current are no longer second-order effects. The outcome of gate-induced drain leakage (GIDL) is effortlessly visible designs, such as DRAM and low-power SRAM. All these outcomes cannot be overlooked as it will lead to non-functional DRAM, SRAM or any other circuit. Reducing the supply voltage which is now not a feasible solution in respect to stability of the SRAMs & reduce the supply voltage the stability also disturbs. Power management is also a challenge in mobile applications. In this paper we have used leakage reduction technique to reduce the leakage power which reduce the leakage power from 40%-50% for the SRAM cell at 45nm technology.
Design and Analysis of Two Low-Power SRAM Cell Structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
In this paper, two Static Random Access Memory (SRAM) cells that reduce the static power dissipation due to gate and sub-threshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation.
Comparative Analysis of Low Leakage SRAM Cell at 32nm Technology
International Journal of Computer Applications, 2016
Continuous scaling of the transistor size and reduction of the operating voltage has led to a significant performance improvement of integrated circuits. Low power consumption and smaller area are the most important criteria for the fabrication of DSP systems. Static random access memories (SRAMs) consist of almost 90% of very large scale integrated (VLSI) circuits. The ever-increasing demand for larger data storage capacity has driven the fabrication technology and memory development toward more compact design rules and, consequently, toward higher storage densities. This paper deals with design of low power static random-access memory (RAM) cells and peripheral circuits for standalone RAMs, in 32nm focusing on stable operation and reduced leakage power dissipation. The work is carried out on Tanner Tool version 13 at 32nm technology.
Subthreshold leakage current reduction techniques for static random access memory
Smart Structures, Devices, and Systems II, 2005
The two main sources of power dissipation in CMOS circuits are dynamic and static power dissipation. Static power dissipation is due to leakage current when the transistor is normally off. The improvement in technology scaling has introduced very large subthreshold leakage current, therefore careful design techniques are very important in order to reduce subthreshold leakage current for low power design. Leakage current occurs in both active and standby modes. It is recommended to switch off the leakage current when the circuit is in standby mode, however it is not always possible to shut off the leakage current completely during this mode. Unlike gate leakage, subthreshold leakage cannot be solved by MOS structures nor by introducing new material. One of the feasible solutions is by combinational use of Low-V t transistors for its high-speed capability and High-V t transistors for very small leakage current. Multi-Threshold CMOS (MTCMOS) and Variable-Threshold CMOS (VTCMOS) are biasing techniques that uses combinations of different threshold voltage and are suitable for SRAM design. Ideally the larger the threshold level the lower the leakage current, however, one must decide the optimum value of threshold level between the power switch (High-V t devices) and (Low-V t devices), as recovery delay tends to increase in higher threshold level. The full paper will discuss the design and performance of SRAM implemented using MTCMOS and VTCMOS biasing techniques. An improved sensing amplifier in the memory cell was incorporated to enhance the circuit performance.
An Ultra-low-power Static Random-Access Memory Cell Using Tunneling Field Effect Transistor
International Journal of Engineering, 2020
In this research article, an Ultra-low-power 1-bit SRAM cell is introduced using Tunneling Field Effect Transistor (TFET). This paper investigates feasible 6T SRAM configurations on improved N-type and P-type TFETs integrated on both InAs (Homojunction) and GaSb-InAs (Heterojunction) platforms. The voltage transfer characteristics and basic parameters of both Homo and Heterojunctions are examined and compared. The proposed TFET based SRAM enhances the stability in the hold, read, and write operations. This work evaluates the potential of TFET which can replace MOSFET due to the improved performance with low-power consumption, high speed, low sub-threshold slope, and supply voltage (VDD = 0.2 V). The results are correlated with CMOS 32nm technology. The proposed SRAM TFET cell is implemented using 30nm technology and simulated using an H-SPICE simulator with the help of Verilog-A models. The proposed SRAM TFET cell architecture achieves low power dissipation and attains high performance as compared to the CMOS and FINFET.
Deep sub-micron SRAM design for low leakage
2010
This paper deals with design opportunities of Static Random Access Memory (SRAM) for low power consumption. Initially three major leakage current components are reviewed and then for a 6T SRAM cell, some of the leakage current reduction techniques are discussed. Finally double finger latch is analyzed and compared with single finger latch which shows reduction in sub threshold leakage current.
Ultra-low leakage SRAM design with sub-32 nm tunnel FETs for low standby power applications
Micro & Nano Letters, 2016
Tunnel-Field-Effect Transistors (TFETs) operate by quantum band-to-band tunneling and display a steeper subthreshold slope than MOSFETs which substantially diminishes the standby current. This work explores the TFETbased SRAM utilization for Low STandby Power (LSTP) applications. We propose an 8T TFET SRAM cell operating at V DD =1V, which, in contrast to other 6T TFET SRAMs, is write-disturb-and half-selection-free. Simulations based on 30nm p-and n-TFETs models relying on I D , C GS , C GD vs. V GS , and V DS look-up tables extracted from TCAD, indicate that the proposed cell has a Read SNM and a Write SNM of 120mV and 200mV, respectively, which are well above state of the art values repotted in the literature. When utilized in an 128x128bit memory array the proposed cell enables read and write operation at 3.84GHz and 806MHz, respectively, and a cell leakage of less than 2fA/bit, which makes it an excellent choice for IoT applications.
IEEE Journal of Solid-state Circuits, 2008
Growing demand for high-performance multi-media processor in handheld devices continues to drive the need for large embedded SRAM with low power consumption. The low-power requirement has often been addressed by compromising SRAM performance through the adoption of lower supply voltage and slower performing transistors with low leakage. Supply voltage scaling in large SRAM has not kept pace with technology scaling due to reduced SRAM cell stability and write margin . Many circuit techniques have been proposed to expand design margins for low-voltage operation while reducing leakage current at standby mode. In this work, we report an SRAM design in a 65nm ultralow-power (ULP) CMOS process . Co-optimization between process technology and circuit design allowed us to achieve fast SRAM access at nominal operating voltage. A large design window in operating voltage along with integrated leakage reduction schemes provides flexibility for both active power management and leakage reduction through dynamic voltage scaling.
Ultra low voltage and low power Static Random Access Memory design using average 6 . 5 T technique
2015
Power Stringent Static Random Access Memory (SRAM) design is very much essential in embedded systems such as biomedical implants, automotive electronics and energy harvesting devices in which battery life, input power and execution delay are of main concern. With reduced supply voltage, SRAM cell design will go through severe stability issues. In this paper, we present a highly stable average nT SRAM cell for ultra-low power in 125nm technology. The distinct difference between the proposed technique and other conventional methods is about the data independent leakage in the read bit line which is achieved by newly introduced block mask transistors. An average 6.5T SRAM and average 8T SRAM are designed and compared with 6T SRAM, 8T SRAM, 9T SRAM, 10T SRAM and 14T SRAM cells. The result indicates that there is an appreciable decrease in power consumption and delay.