Effects of geometry and temperature cycle on the reliability of WLCSP solder joints (original) (raw)
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Effect of geometry and temperature cycle on the reliability of WLCSP solder joints
IEEE Transactions on Components and Packaging Technologies, 2000
The wafer level-chip-scale package (WLCSP) is designed to have external dimensions equal to that of the silicon device. This new package type is an extension of flip chip packaging technology to standard surface mount technology. The package has been targeted for low pin count (less than 30) and has high volume applications such as cellular phones, hand-held PDAs, etc. The WL-CSP is typically used without underfill and so solder joint reliability is a prime concern. Thus it is imperative to have a good understanding of the various design parameters of the package that affect the reliability of the solder joint. This paper presents the effect of geometrical parameters such as die size, die thickness, solder joint diameter and height on the reliability of solder joints. The effects of different dwell times, temperature range and ramp rates on the reliability of the solder joints is also studied by applying different temperature cycles to the package.
Reliability of soldered joints in CSPs of various designs and mounting conditions
IEEE Transactions on Components and Packaging Technologies, 2001
The chip size package (CSP) is being used in various portable electronic products recently. Further evaluation of the reliability of its soldered joints is required all the more now because those soldered joints are invisible. This study focused on the thermal fatigue life of soldered joints in the CSP. CSPs were mounted on printed circuit boards (PCBs) in various configurations and mounting conditions, and underwent thermal cycle testing. Then, the fatigue lives of their soldered joints were compared. As a result, the following two facts became apparent. First, reflowing at a 210 C peak tends to result in failures that may be derived from poor wetting between solder and pad, in cases where the CSP is mounted on a nickel and gold plated pad. And second, the size of the soldered joint has a great influence on its fatigue life. The larger the soldered joints that we made, the longer fatigue life they indicated. A finite element method (FEM) analysis of those mounted structures was also executed. Viscoplastic (creep and plastic) property of solder was evaluated to compute equivalent inelastic strain occurring in the joints. A parameter in the Coffin-Manson equation is obtained from the computed inelastic strain amplitudes and the experimented actual fatigue lives. This result will enable estimation of the fatigue life of soldered joints of the CSP without actual tests. Index Terms-CSP, FEM analysis, Ni/Au plated pad, reliability, thermal fatigue, Weibull cumulative hazard analysis. I. INTRODUCTION T HE chip size package (CSP) is now becoming one of the main products in the integrated circuit (IC) industry. In recent years, portable electronic products, such as cellular phones, camcorders, and pagers, have been required to be miniaturized, with increased performance. Accordingly, IC packages adopted in these electronic products are gradually being changed. The conventional IC package has outer leads lining its sides only, as seen in the quad flat package (QFP), small outline package (SOP), and so on. However, new types have external terminals arranged on their whole bottom surface, as seen in the ball grid array (BGA) and CSP.
Historically, energy-based solder fatigue life models have been used primarily for PBGA or similar package configurations. In this paper, we extend the energy-based method to newly emerged Wafer Level, Chip Scale Package (WL-CSP). National Semiconductor's micro SMD package family was chosen as the test vehicle. Among all energy- based methods, Darveaux's model is arguably the most popular one due to its well-documented good correlation with the actual tests. To maintain consistency in results, Darveaux suggested that the solder joint be meshed such that the element size in its height direction has fixed value. However, we found in our study that Darveaux's model faired poorly in capturing the package fatigue life, even though the mesh size issue was carefully addressed. In view of the drastic difference in solder ball size between WL-CSP and PBGA, on which Darveaux's model is based, we argue that in addition to the element size in the solder height direction, the...
Improving Solder Joint Reliability of WLP by Means of a Compliant Layer
2006 Thirty-First IEEE/CPMT International Electronics Manufacturing Technology Symposium, 2006
The common structure of a Wafer Level Package (WLP) has direct under-bump-metallization (UBM) and solders bumps attached to a silicon chip. These WLP solder joint connections have a relatively low structural compliance to the silicon chip. Studies have shown that low structural compliance typically result in issues with solder joint reliability and shorter fatigue life under thermal cyclic loading (TMCL). However, the reliability of such WLP assemblies can be improved by introducing a layer of low modulus-based material in between the chip and the UBM/solder bump, also known as a compliant layer. This paper studies the reliability of one instance of a WLP with a compliant layer during TMCL. This study was performed via finite element (FE) modeling and then compared with experimental results.
Optimization of reliability of copper-low-k flip chip package with variable interconnect compliance
2008 58th Electronic Components and Technology Conference, 2008
The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of fine-pitch, large-die Cu/low-k flip chip packages. In this paper, 3D finite element analyses were performed to investigate the reliability of 65nm, 21x21mm 9metal Cu/ low-k, chips with 150um interconnect pitch in a FCBGA package with a 750um die thickness and 1.0mm substrate thickness. Three parametric cases involving different geometries of solder joints were analyze: (A) All 20 rows with spherical solder joints, (B) 10 hourglass joints followed by 10 spherical joints, and (C) 10 spherical joints followed by 10 hourglass joints. The spherical joints are stiffer than the hourglass joints. It was found that Case C gave the lowest inelastic energy dissipation (∆W) for the critical solder joint implying that Case C will have the longest fatigue life. It was also found that Case C gave the lowest maximum stress in the low-k material and it was further shown that reliability will be enhanced with decrease in die thickness and substrate thickness.
High temperature reliability of lead-free solder joints in a flip chip assembly
Journal of Materials Processing Technology, 2012
The visco-plastic behaviour of solder joints of two models of a flip chip FC48D6.3C457DC mounted on a printed circuit board (PCB) via SnAgCu solder is investigated using Anand's model. While the bumps of one of the models are realistic with 6 m thickness of intermetallic compound (IMC) at interconnects of solder and bond pads, the other are made up of conventional bumps without IMC at these interconnects. The solder bump profiles were created using a combination of analytical method and construction geometry. The assembled package on PCB was accelerated thermally cycled (ATC) using IEC standard 60749-25. It was found in the result of the simulation that IMC does not only impact solder joint reliability but also is a key factor of fatigue failure of solder joints. The IMC sandwiched between bond pad at chip side and solder bulk is the most critical and its interface with solder bulk is the most vulnerable site of damage. With reference to our results, it is proposed that non inclusion of IMC in solder joint models composed of Sn-based solder and metalized copper substrate is one of the major causes of the discrepancy on solder joint fatigue life predicted using finite element modelling and the one obtained through experimental investigation.
2017
This study treats the reliability of solder joints of electronic assemblies, in terms of methodology of evaluation, applicable stress tests and analyses. This study is focused on lead-free solder alloys and describes the solder joint microstructure and its changes caused by thermal stresses, ATC (Accelerated Thermal Cycling) and thermal shock, which cause thermomechanical stresses to the solder joints. In particular, this study compares the different stresses caused by the fast and slow thermal swings. Another topic is a revision of the criteria to evaluate the solder joints on the base of the link between the stress tests and the conditions of the product life. Finally, a proposal for the stress tests and the evaluation criteria is described.
Impact of solder pad size on solder joint reliability in flip chip PBGA packages
1999
A variety of package parameters impact package reliability. One of the parameters that does not get much attention is the variations in package design that are assembly and vendor related. It was shown in this study that the solder pad size plays a big role in solder joint reliability. The difference in solder pad size due to different vendors and processes can affect the reliability considerably. In certain cases, the pad size effect can be so significant that it will override the effect of substrate thickness. Our work indicates that in order to obtain good correlations between predictive engineering results and reliability tests data, this factor should not be ignored. In this paper, finite element analysis was used to study the impact of substrate thickness on solder reliability for flip-chip PBGA (plastic ball grid array) packages. The simulation results were experimentally validated with moire interferometry. Both numerical and experimental results indicated that better solder reliability could be achieved by using thicker substrate. However, the size of BGA solder pad was found to be crucial to BGA life. In order to achieve higher C5 (controlled collapse chip carrier connection) reliability, a larger solder pad is preferred
Parametric finite element Analysis of solder joint reliability of flip chip on board
… Technology Conference, 1998. Proceedings of 2nd, 1998
Numerous studies have indicated that by encapsulating the solder joint with underfill material, the reliability of flip chip on board (FCOB) assemblies can be effectively enhanced. Typical manufacturing process for FCOB assembly with underfill, however, involves long throughput time and additional equipment sets which are undesirable for high volume manufacturing environments. Hence, desigdprocess simplification if not total elimination of underfill from the conventional FCOB assemblies that can directly result in productivity gain should be considered. A comprehensive parametric finite element analysis has been conducted to assess the feasibility of FCOB structures with partial underfill (i.e. only the peripheral joints are encapsulated with underfill material.) The effects of some critical design parameters such as die size, joint height, joint diameter, joint pitch, printed circuit board (PCB) thickness and material properties of underfill on the solder joint reliability of FCOB structure were investigated in this study. Two-dimensional nonlinear plane strain finite element models of FCOB package are employed. Moire and IR Fizeau interferometry technique are used to measure the thermal deformation of the FCOB for model validation. Elasto-plastic deformation behaviors of solder were simulated under thermal cyclic loading from-55 "C to 125 "C. Maximum effective elastic and plastic strains of the solder joint were calculated and used as the indicator for determining the solder joint reliability of the structures.