Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits (original) (raw)

Promising directions in hardware design verification

2002

Ensuring the functional correctness of hardware early in the design cycle is crucial for both economic and methodological reasons. However, current verification techniques are inadequate for industrial designs. Formal verification techniques are exhaustive but do not scale; partial verification techniques based on simulation scale well but are not exhaustive. This paper discusses promising approaches for improving the scalability of formal verification and comprehensiveness of partial verification.

A Decomposition Workflow for Integrated Circuit Verification and Validation

Journal of Hardware and Systems Security

This paper reviews a developed integrated circuit (IC) decomposition workflow that can be leveraged for extracting design files and performing advanced verification and validation techniques on fabricated chips. In this work, a commercial 130-nm microcontroller is delayered and imaged to recreate the full design stack-up. Using MicroNet's Pix2Net, the features for each layer are extracted allowing a GDSII file to be generated and design netlists for target components to be recovered. The full decomposition process is executed on both the read only memory (ROM) array and universal serial communications interface (USCI) of the microcontroller to recover the layout GDSII and circuit netlist. A single-precision floating point unit (FPU) test article is used to incorporate a spectrum of error types into the design layout, thus creating a set of test articles with obfuscated errors. Once the netlists for each of the modified designs are extracted, formal verification techniques are applied to each netlist, thus illuminating the errors originally inserted into the layout. The extracted netlists are then converted into register transfer level (RTL) representations and simulated with the original design verification testbench.

Using formal specifications for functional validation of hardware designs

Design & Test of Computers, IEEE, 2002

Formal specifications can help resolve both ambiguity issues and correctness problems in verifying complex hardware designs. This new methodology shows how specifications can also help design productivity by automating many procedures that are now done manually. Input sequences, output assertions, and a simulation coverage metric for the design under verification are all generated directly from the specification

Survey on Design Automation and Verification for VLSI Circuits

International Journal of Research and Analytical Reviews (IJRAR), 2023

The field of Very Large-Scale Integration (VLSI) has developed throughout the course of recent many years and has turned into a critical empowering innovation for an extensive variety of current gadgets. The integration of millions of transistors onto a single chip in VLSI design poses a significant challenge in terms of verification complexity. Design automation and verification has emerged as a significant area of research and development An overview of design automation and verification for VLSI circuit design is the goal of this paper. We'll talk about the difficulties encountered during the design process and how design automation and verification methods can be used to overcome them. also look at the many tools, methods, and processes utilized in VLSI circuit design for design automation and verification. Finally, we will look at recent advancements in this area and the forecast for design automation and circuit verification for VLSI devices in the future

From Circuit Simulation to Circuit Verification: An Internal + Boundary- Scan-Based Solution

2000

Matching the results obtained from circuit simulation with those extracted from circuit functioning is a common stage of the final verification process. Many current verification techniques use the I/O vectors produced during functional and / or timing simulation, for creating the test vectors to be applied / compared against the circuit responses. Techniques that are more complete include extracting the values of internal sequential nodes and comparing these using internal scans. This paper describes such a solution for verifying digital designs implemented in currently commercial available CPLDs. The test program is automatically generated from information that encompasses the design & development phase, namely: the file containing the results from simulation, the BSDL file, an internal scan chain description file, and one file containing the user options.

High Level Design Validation: Current Practices and Future Directions

2004

With the increasing complexity of VLSI design and time-to-market pressures, two major paradigms have emerged to address the difficulties currently being faced by the industry. They are: (1) the use of higher levels of design abstraction and (2) efficient and seamless design reuse. The design and modeling of a chip at higher levels of design abstraction brings with it additional burdens of validation, verification and testing at these levels.

The practical verification of microprocessor designs

COMPCON Spring '91 Digest of Papers

Hardware verification is a technique for reducing the number of design faults in a device. Even though much research has been done in the area, verification is still not used by circuit designers. This paper examines an engineering methodology f o r verifying micmpwcessors, describes two case studies using this methodology, and discusses research aimed at integmting verification with VLSI CAD tools. We believe that these steps are necessary if verification is to be used by engineers.

Embedding hardware verification within a commercial design framework

Lecture Notes in Computer Science, 1993

A methodology for verifying complex circuits is presented, based on a strong coupling of design veri cation with the hierarchical design process. This goal has been achieved by integrating MEPHISTO, a tool for semi-automated hardware veri cation, into a commercial design framework. MEPHISTO decomposes the veri cation goal by a set of hardware-speci c proof tactics and provides strategies for synthesizing pre-veri ed regular components. In case of erroneous implementations, MEPHISTO aids the designer in debugging the circuit by generating a counter model, i.e. input stimuli where speci cation and implementation behave di erently.