High Level Design Validation: Current Practices and Future Directions (original) (raw)
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Design and verification languages
… of Computer Science Columbia University, New …, 2004
After a few decades of research and experimentation, registertransfer dialects of two standard languages-Verilog and VHDL-have emerged as the industry standard starting point for automatic large-scale digital integrated circuit synthesis. Writing RTL descriptions of hardware remains a largely human process and hence the clarity, precision, and ease with which such descriptions can be coded correctly has a profound impact on the quality of the final product and the speed with which the design can be created.
A formal equivalence checking methodology for Simulink and Register Transfer Level designs
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012
Driven by the increase in complexity of design, timeto-market pressure and the need for a high level of collaboration between multiple discipline teams in a project, model based design has become the inevitable choice for IC Design projects. High-level models are being substantially used as the reference for implementation of the Register Transfer Level (RTL) counterpart of the designs. In that respect, Matlab/Simulink is one of the adopted high level modeling platforms in the IC design industry. However, checking the formal equivalence of the models with their RTL counterparts is still an area of interest to be investigated. In this study, a methodology addressing that matter is proposed. Simulink models of interest in this paper comprise built-in Simulink blocks, Stateflow blocks modeling the state machines, and user-defined blocks. Proposed methodology utilizes Simulink's Hardware Design Language (HDL) Coder and Real Time Workshop (RTW) tools, Mentor Graphics' Catapult, and Synopsys' Formality in the flow. Building of the methodology is explained with a simple example. Then the methodology is applied to multiple designs, including Advanced Encryption Standard (AES) to verify its applicability.
Specification and verification of system-level hardware designs using time diagrams
1993 European Conference on Design Automation with the European Event in ASIC Design
In this paper we present U novel cipprotic*li to the specification and verification of system-level Ii(irdwre designs. It is based on Timing Diagrams, ii griipliicwl spec +cation langriagc with an intititive semrinrics, wlircli is especicilly uppropriate f o r tlic' description of asynchronous distributed systems ~ticli (is liiirdwtrre designs. Timing Dirrgroms and their setnrrntics [ire formally defined based on (I transintion to Tempr(i1 Logic. It is shown that for the resulting y p e of forrniiios there is an efficient modelchecking procediire, tlrris allowing fully automatic verification of liardwiire designs. I I system-level chip-level I qusli tative time quantitative time I 0
Formal verification in hardware design
ACM Transactions on Design Automation of Electronic Systems, 1999
In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing.There are two main aspects to the application of formal methods in a design process: the formal framework used to specify desired properties of a design and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between ω-regular languages. The verification techniques presented include model checking, automata-theoretic techniques, automated theorem proving, and approaches that integrate the above methods.In order to provide insight in...
Citeseer
The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stages can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses upon a technique that integrates the best characteristics of both simulation and formal verification methods to provide an effective design validation tool, referred as Integrated Design Validation (IDV). The novelty in this approach consists of three components, circuit complexity analysis, partitioning based on design hierarchy, and coverage analysis. The circuit complexity analyzer and partitioning decompose a large design into subcomponents and feed sub-components to different verification and/or simulation tools based upon known existing strengths of modern verification and simulation tools. The coverage analysis unit computes the coverage of design validation and improves the coverage by further partitioning. Various simulation and verification tools comprising IDV are evaluated and an example is used to illustrate the overall validation process. The overall process successfully validates the example to a high coverage rate within a short time. The experimental result shows that our approach is a very promising design validation method.
Promising directions in hardware design verification
2002
Ensuring the functional correctness of hardware early in the design cycle is crucial for both economic and methodological reasons. However, current verification techniques are inadequate for industrial designs. Formal verification techniques are exhaustive but do not scale; partial verification techniques based on simulation scale well but are not exhaustive. This paper discusses promising approaches for improving the scalability of formal verification and comprehensiveness of partial verification.
Hierarchical and Incremental Verification for System Level Design: Challenges and Accomplishments
2003
This panel will focus on two problems in formal and semiformalverification of co-design models. First one can be categorizedas Hierarchical verification or compositional verification. The second one is Incremental verification. Advances and challengesin both of these are important for realization of verificationstrategies for reasonable sized models, including hardware models, as well as hardware/software co-design models. This short positionpaper explains the MEMOCODE committee's view of theseproblems, followed by ...
A unified approach for combining different formalisms for hardware verification
Lecture Notes in Computer Science, 1996
Model Checking as the predominant technique for automatically verifying circuits su ers from the well-known state explosion problem. This hinders the veri cation of circuits which contain non-trivial data paths. Recently, it has been shown that for those circuits it may be useful to separate the control and data part prior to veri cation. This paper is also based on this idea and presents an approach for combining various proof approaches like model checking and theorem proving in a unifying framework. In contrast to other approaches, special proof procedures are available to verify circuits with data sensitive controllers, where a bidirectional signal ow between controller and data path can be found. Generic circuits can be veri ed by induction or by model checking nite instantiations. By giving the system`proof hints', also the veri cation e ort for model checking based proofs can be considerably reduced in many cases. The paper presents an introduction to the di erent proof strategies as well as an algorithm for their combination. The underlying C@S system also allows the e ciency evaluation of di erent approaches to verify the same circuits. This is shown in di erent case studies, demonstrating the tradeo between interaction and veri able circuit size.