Modeling Injection of Electrical Fast Transients Into Power and IO Pins of ICs (original) (raw)

Modeling of Power Supply Transients for EMI Compliance in Digital Systems

This paper addresses the modeling of power supply voltage transients in digital systems, in order to estimate the system's tolerance to this disturbance, in order to demonstrate EMI/EMC standard compliance. Electrical simulation is extensively used to demonstrate the possibility of exploiting the duality between time excitation and delay response, for combinational CUT (Circuit Under Test). We refer this as the "accordion" effect. The proposed technique makes use of concepts derived from the VLV (Very Low Voltage) testing and V DD ramp testing techniques. Two regions of operation under ∆V DD voltage drop are defined through the threshold power supply voltage, V DDth , parameter. Electrical simulation supports the method, recently proposed, to perform fault simulation either by using faulty delays (defect size proportional to ∆V DD magnitude) in the CUT and nominal time excitation rate, or by using a fault-free CUT description and faster test application times. Furthermore, for sequential circuits it is shown that the tolerance to ∆V DD disturbances may be significantly lower than the one observed in combinational CUTs, due to de-synchronization effects in storage elements.

Modeling timing variations in digital logic circuits due to electrical fast transients

2013 IEEE International Symposium on Electromagnetic Compatibility, 2013

Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, like an electrical fast transient (EFT). Soft failures in these cases are often caused by timing errors in the IC, for example when delays through logic become too large to meet internal timing constraints. Methods are needed to predict when these failures will occur. A closedform expression is proposed in this paper to predict the change in propagation delay through logic as a result of an EFT on the IC power supply. The expression uses process parameters that can be found from SPICE models of FETs within the IC or through external measurements of the IC when SPICE models are unavailable. The model is used to predict the frequency of a CMOS ring oscillator manufactured in 0.5 um technology. Predicted results closely match those found through measurements with a maximum relative error of approximately 1%.

Experimental Investigation of the ESD Sensitivity of an 8-Bit Microcontroller

2007 IEEE International Symposium on Electromagnetic Compatibility, 2007

In this paper, the susceptibility of an 8-bit microcontroller to electrostatic discharge (ESD) and electrically fast transients was tested by injecting currents through a capacitive probe into the microcontroller package pins. The reaction of the microcontroller to discharges with different rise times and polarities were investigated by measuring the voltage on the tested pins and by observing the microcontroller's clock output. Susceptibility varied significantly when injecting to one pin compared to another. Interestingly, the clock was more sensitive to currents injected into I/O pins than into pins directly related to the clock (e.g. EXTAL). Further work is underway to explain the causes of susceptibility inside the IC.

Modeling Single Event Transients in Advanced Devices and ICs

IEEE Transactions on Nuclear Science

The ability for Single Event Transients (SETs) to induce soft errors in Integrated Circuits (ICs) was predicted for the first time by Wallmark and Marcus in the early 60’s and was confirmed to be a serious issue thirty years later. In the 90’s microelectronic technologies reached the “deep submicron” era, allowing high density ICs working at frequencies faster than hundreds of MHz. This new paradigm changed the status of SETs to become a major source of reliability losses. Huge efforts have thus been made to characterize SETs in microelectronics, either using experiments or by simulation, in order to reveal key factors leading to SET occurrence, propagation and capture in modern ICs. In this context, modeling and simulation are of primary importance to get accurate SET predictions. This paper focuses on modeling SETs in innovative electronic devices which involves modeling steps at different scales, from ionizing particle to circuit response. After a brief review of the state-of-the...

Susceptibility of Integrated Circuits to Electrostatic Discharge

2012

The components that are considered fairly rugged can be damaged by electrostatic discharge (ESD). Bipolar transistors, the earliest of the solid state amplifiers, are not immune to ESD, though less susceptible. Devices manufactured using metal oxide semiconductor (MOS) technology can be easily damaged due to ESD but some of the newer high speed components can be ruined with as little as 3 volts. The integrated circuits (IC) are susceptible to ESD due to its small size and unavailability of larger area to dissipate the excess energy. The susceptibility of IC’s can be determined by various ESD stress tests. The different ESD stress modes on an input or output pin which is Pin-to-VSS, Pin-to-VDD are used to test an IC. The IC after ESD stresses may undergo damage not only in the input/output circuits or devices, but also in the internal circuits. The effects of ESD on various logic gates belonging to both transistor-transistor logic (TTL) and Complementary MOS (CMOS) logic families hav...

Modeling of IC power supply and I/O ports from measurements

2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems, 2009

This paper addresses the generation of behavioral models of digital ICs for signal and power integrity simulations. The proposed models are obtained by external port measurements and by the combined application of specialized state-of-the-art modeling techniques. The proposed approach is demonstrated on the I/O buffers and the core power supply ports of a commercial 90nm flash memory.

On-Chip Transient Detection Circuit for System-Level ESD Protection in CMOS Integrated Circuits to Meet Electromagnetic Compatibility Regulation

IEEE Transactions on Electromagnetic Compatibility, 2000

A new on-chip transient detection circuit for systemlevel electrostatic discharge (ESD) protection is proposed. The circuit performance to detect different positive and negative fast electrical transients has been investigated by the HSPICE simulator and verified in a silicon chip. The experimental results in a 0.13-µm CMOS integrated circuit (IC) have confirmed that the proposed on-chip transient detection circuit can be used to detect fast electrical transients during the system-level ESD events. The proposed transient detection circuit can be further combined with the poweron reset circuit to improve the immunity of the CMOS IC products against system-level ESD stress.

Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models

2002

A device testing method called Transient Signal Analysis (TSA) is subjected to elements of a real process and testing environment in this paper. Simulation experiments are designed to determine the effects of process skew (obtained from measured parameters of a real process) on the accuracy of TSA in estimating path delays from power supply IDDT and VDDT waveforms. The circuit model is designed to test TSA under deep submicron process models that incorporate advanced parameters such as transistor Vt width dependencies. Modeling elements of a testing environment including the probe card are subsequently introduced as a means of evaluating the effects of tester measurement noise in an actual implementation.

Power Supply- and Temperature-Aware I/O Buffer Model for Signal-Power Integrity Simulation

Mathematical Problems in Engineering

This paper presents the development and evaluation of a large-signal equivalent circuit model that accounts for the power supply fluctuation and temperature variation of I/O buffers circuit designed based on the fully depleted silicon on insulator (FDSOI) 28 nm process for signal-power integrity (SPI) simulation. A solid electrical analysis based on the working mechanisms of the nominal I/O buffer information specification- (IBIS-) like model is presented to support the derivation of an accurate and computationally efficient behavioral model that captures the essential effects of the power supply bouncing under temperature variation. The formulation and extraction of the Lagrange interpolating polynomial are investigated to extend the nominal equivalent circuit model. The generated behavioral model is implemented using the Newton-Neville’s formula and validated in simultaneous switching output buffers (SSO) scenario under temperature variation. The numerical results show a good pred...