Modeling Single Event Transients in Advanced Devices and ICs (original) (raw)
Related papers
Accurate and computer efficient modelling of single event transients in CMOS circuits
IET Circuits, Devices & Systems, 2007
A new analytical modelling approach to evaluate the impact of single event transients (SETs) on CMOS circuits has been developed. The model allows evaluation of transient pulse amplitude and width (duration) at the logic level, without the need to run circuit level (Spice-like) simulations. The SET mechanism in MOS circuits is normally investigated by Spice-like circuit simulation. The problem is that electrical simulation is time-consuming and must be performed for each different circuit topology, incident particle and track. The availability of a simple model at the logic gate level may greatly improve circuit sensitivity analysis. The electrical response of a circuit to an ionising particle hit depends on many parameters, such as circuit topology, circuit geometry and waveform shape of the charge injection mechanism. The proposed analytical model, which is accurate and computer efficient, captures these transistor-level effects of ionising particle hits and models them to the logic level of abstraction. The key idea is to exploit a model that allows the rapid determination of the sensitivity of any logic gate in a CMOS circuit, without the need to run circuit simulations. The model predicts whether or not a particle hit generates a SET, which may propagate to the next logic gate or memory element, making possible to analyse the sensitivity of each node in a complex circuit. Model derivation is strongly related to circuit electrical behaviour, being consistent with technology scaling. The model is suitable for integration into CAD tools, intending to make automated evaluation of circuit sensitivity to SET possible, as well as automated estimation of soft error rate.
IEEE Transactions on Nuclear Science, 2000
This paper presents a SET predictive methodology based on coupled MUSCA SEP3 and electrical simulations (CA-DENCE tool). The method is validated by SET measurements on an inverters chain based on 65-nm bulk CMOS technology, and two designs were considered (respectively for same-well and separate-well designs). These methodologies have been validated in the case of 1000 inverters chain and for heavy ions and demonstrate the impact of the quenching effect. Furthermore, both the designs were considered and the analyses are consistent with experiments and this allows for identification of the quenching effect as the main mechanism responsible for the difference in SET sensitivity. However, the modeling approach can be also used for other logical cells or/and complex radiation environments, to determine SET cross sections, SET cartographies and SET characteristics. This method is applied to SEU analyses, i.e., SBU (Single Bit Upset) and MCU (Multiple Cell Upset) for 65-nm bulk SRAM memory and neutron/proton SET modeling.
Single-Event Upsets in Microelectronics
MRS Bulletin, 2003
This article introduces the February 2003 issue of MRS Bulletin on “Single-Event Upsets (SEUs) in Microelectronics.” These radiation effects in devices and circuits have been recognized in recent years as a key reliability concern for many current and future silicon-based technologies. This introduction sets the scope for critical discussions on this subject. The articles in the issue reflect the interdisciplinary nature of SEU research. The contributing authors include experts from several specializations: technology reliability, materials science, device physics, circuit designs, and theoretical and experimental nuclear physics. We review the current understanding of SEU problems from the perspectives of radiation physics, circuit design issues, and global technology developments. The discussions cover the key areas of modeling, circuit analyses, accelerator tests and experiments, basic nuclear data, and environmental neutron measurements.
Modeling the sensitivity of CMOS circuits to radiation induced single event transients
Microelectronics Reliability, 2008
An accurate and computer efficient analytical model for the evaluation of integrated circuit sensitivity to radiation induced single event transients is presented. The key idea of the work is to exploit a model that allows the rapid determination of the sensitivity of any MOS circuit to single event transients (SETs), without the need to run circuit level simulations. To accomplish this task, both single event transient generation and its propagation through circuit logic stages are characterized and modeled. The model predicts whether or not a particle hit generates a transient pulse which may propagate to the next logic gate or memory element. The electrical masking (attenuation) of the transient pulse as it propagates through each stage of logic until it reaches a memory element is also modeled. Model derivation is in strong relation with circuit electrical behavior, being consistent with technology scaling. The model is suitable for integration into CAD-Tools, intending to make automated evaluation of circuit sensitivity to SEU possible.
Single-Event Transient Analysis in High Speed Circuits
2011 International Symposium on Electronic System Design, 2011
The effect of Single-Event Transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of a combinational part of a circuit may propagate as a transient pulse at the input of a flip-flop and consequently latches in the flip-flop; thus generating a soft-error. When an SET is combined with a transition at a node (i.e., dynamic behavior of that node) along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a circuit flip-flop. Using the Probability Density Function (PDF) of an SET, this paper proposes a statistical method to compute the probability of soft-errors caused by SETs considering dynamic behavior of a circuit.
Modeling, Analyzing, and Abstracting Single Event Transient Propagation at Gate Level
—Soft errors have become one of the most challenging issues that impact the reliability of modern microelectronic systems at terrestrial altitudes. A new methodology to abstract, model, and analyze Single Event Transient (SET) propagation at different abstraction levels (transistor and gate level) is proposed. Transistor level characterization libraries are developed to abstract the impact of input patterns, pulse polarity, and propagation paths characteristics on the SET duration. Thereafter, these libraries are utilized to analyze SET pulse propagation at gate level using MDG model checker. We have implemented the proposed method on different ISCAS85 benchmark combinational circuits. The proposed methodology is orders of magnitude faster than circuit level simulations. Moreover, we have developed gate level characterization libraries to abstract SET pulse propagation behavior at the gate level.
Measuring and Modeling Single Event Transients in 12-nm Inverters
IEEE Transactions on Nuclear Science, 2022
In this article, we present a unique method of measuring single-event transient (SET) sensitivity in 12-nm FinFET technology. A test structure is presented that approximately measures the length of SETs using flip-flop shift registers with clock inputs driven by an inverter chain. The test structure was irradiated with ions at linear energy transfers (LETs) of 4.0, 5.6, 10.4, and 17.9 MeV-cm 2 /mg, and the cross sections of SET pulses measured down to 12.7 ps are presented. The experimental results are interpreted using a modeling methodology that combines TCAD and radiation effect simulations to capture the SET physics, and SPICE simulations to model the SETs in a circuit. The modeling shows that only ion strikes on the fin structure of the transistor would result in enough charge collected to produce SETs, while strikes in the subfin and substrate do not result in enough charge collected to produce measurable transients. Comparisons of the cumulative cross sections obtained from the experiment and from the simulations validate the modeling methodology presented.
Single-Event Upset Analysis and Protection in High Speed Circuits
Eleventh IEEE European Test Symposium (ETS'06), 2006
The effect of Single-Event Transients (SETs) (at a combinational node of a design) on the system reliability is becoming a big concern for ICs manufactured using advanced technologies. An SET at a node of combinational part may cause a transient pulse at the input of a flip-flop and consequently is latched in the flip-flop and generates a soft-error. When an SET conjoined with a transition at a node along a critical path of the combinational part of a design, a transient delay fault may occur at the input of a flip-flop. On the other hand, increasing pipeline depth and using low power techniques such as multi-level power supply, and multi-threshold transistor convert almost all paths in a circuit to critical ones. Thus, studying the behavior of the SET in these kinds of circuits needs special attention. This paper studies the dynamic behavior of a circuit with massive critical paths in the presence of an SET. We also propose a novel flip-flop architecture to mitigate the effects of such SETs in combinational circuits. Furthermore, the proposed architecture can tolerant a Single Event Upset (SEU) caused by particle strike on the internal nodes of a flip-flop.
IEEE Transactions on Nuclear Science, 2014
This work presents a SEL modeling based on physical simulations performed by MUSCA SEP3 and electrical simulations. This approach leads to use the layout description and process information (from TCAD, design or ITRS hypotheses) of a CMOS inverter cell to extract the characteristics of the parasitic circuitry. This approach is totally compatible with the Monte Carlo tool, MUSCA SEP3, with the aim to propose estimations of SEL susceptibility as well in terms of cross section, as sensitivity mapping. The latchup transient response is calculated and compared with heavy ion and TPA experimental measurements. The good agreements are shown in terms of latchup current and the electrical steps leading to the SEL occurrence. Complementary comparisons of SEL sensitive area mapping for TPA irradiation are presented and assessed. The ability of the model to take into account the temperature impact on the SEL sensitivity is presented and discussed.
Layout-oriented simulation of non-destructive single event effects in CMOS IC blocks
2009 European Conference on Radiation and Its Effects on Components and Systems, 2009
This paper presents a tool based on a two dimensional charge-collection simulation to study non-destructive single event effects in CMOS IC blocks. The interaction between the radiation particle and the p-n junctions is modeled at circuit level with a set of parasitic currents, which are injected into the nodes corresponding to the geometrical areas at or near the point where the particle hits the IC. A drift-diffusion model is used to obtain parasitic currents waveforms. By means of circuit simulations, single event transients and single event upsets can be obtained for different collision positions. From simulation results, a map can be drawn, showing the sensitivity to single events of different layout regions. By comparing sensitivity maps, the designer can choose the most robust layout with respect to single event effects. Layout design guidelines are proposed to improve radiation hardness.