Bit-level processor array architecture for flexible string matching (original) (raw)
Processor Array Architectures for Flexible Approximate String Matching
In this paper, we present linear processor array architectures for flexible approximate string matching. These architectures are based on parallel realization of dynamic programming and non-deterministic finite automaton algorithms. The algorithms consist of two phases, i.e. preprocessing and searching. Then, starting from the data dependence graphs of the searching phase, parallel algorithms are derived, which can be realized directly onto special purpose processor array architectures for approximate string matching. Further, the preprocessing phase is also accommodated onto the same processor array designs. Finally, the proposed architectures support flexible patterns i.e. patterns with a ''don't care'' symbol, patterns with a complement symbol and patterns with a class symbol.
A Programmable Array Processor Architecture for Flexible Approximate String Matching Algorithms
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array processor architecture for a wide variety of approximate string matching algorithms to gain high performance at low cost. Further, we describe the architecture of the array and the architecture of the cell in detail in order to efficiently implement for both the preprocessing and searching phases of most string matching algorithms. Further, the architecture performs approximate string matching for complex patterns that contain don't care, complement and classes symbols. We also simulate and evaluate the proposed architecture on a field programmable gate array (FPGA) device using the JHDL tool for synthesis and the Xilinx Foundation tools for mapping, placement, and routing. Finally, our programmable implementation achieves about 8-340 times faster execution than a desktop computer with a Pentium 4 3.5 GHz for all algorithms when the length of the pattern is 1024.
20th International Parallel and Distributed Processing Symposium, IPDPS 2006, 2006
Approximate string matching problem is a common and often repeated task in information retrieval and bioinformatics. This paper proposes a generic design of a programmable array processor architecture for a wide variety of approximate string matching algorithms to gain high performance at low cost. Further, we describe the architecture of the array and the architecture of the cell in detail in order to efficiently implement for both the preprocessing and searching phases of most string matching algorithms. Further, the architecture performs approximate string matching for complex patterns that contain don't care, complement and classes symbols. We also implement and evaluate the proposed architecture on a field programmable gate array (FPGA) device using the JHDL tool for synthesis and the Xilinx Foundation tools for mapping, placement, and routing. Finally, our programmable implementation achieves about 9-340 times faster than a desktop computer with a Pentium 4 3.5 GHz for all algorithms when the length of the pattern is 1024.
2011
String matching has become essential for modern computers. It is used in many applications ranging from data mining to network security. A problem is that current general purpose computers are no longer fast enough to deal with the ever increasing amounts of data that are passed though them due to the massive increases in network traffic and data storage capacities offered. This paper aims to demonstrate the significant performance gains that can be achieved by employing string matching algorithms directly on hardware using an FPGA, as opposed to the traditional software-only solution. A possible future FPGA-based string matching board that could be installed in current computers is discussed.
A Memory-Efficient and Modular Approach for String Matching on FPGAs
2010
In Network Intrusion Detection Systems (NIDSs), string matching demands exceptionally high performance to match the content of network traffic against a predefined database of malicious patterns. Much work has been done in this field; however, they result in low memory efficiency 1 . Due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-ofthe-art designs cannot support large dictionaries without using high-latency external DRAM. We propose a novel Memory efficient Architecture for large-scale String Matching (MASM), based on pipelined binary search tree. With memory efficiency close to 1 byte/char, MASM can support a dictionary 2 of over 4 MBytes, using a single FPGA device. The architecture can also be easily partitioned, so as to use external SRAM to handle even larger dictionaries of over 8 MBytes. Our implementation results show a sustained throughput of 3.5 Gbps, even when external SRAM is used. The MASM module can be simply duplicated to accept multiple characters per cycle, leading to scalable throughput with respect to the number of characters processed in each cycle. Dictionary update involves only rewriting the memory content, which can be done quickly without reconfiguring the chip.
A keyword match processor architecture using content addressable memory
Proceedings of the 14th ACM Great Lakes symposium on VLSI, 2004
This paper demonstrates a keyword match processor capable of performing fast dictionary search with approximate match capability. Using a content addressable memory with processor element cells, the processor can process arbitrary sized keywords and match input text streams in a single clock cycle. The processor is capable of determining approximate match and providing distance information as well. A 64-word design has been developed using 19000 transistors and it could be expanded to larger sizes easily. Using a modest 0.5 micron process, we are achieving cycle times of 8 ns and the design will scale to smaller feature sizes.
Journal of Microcomputer Applications, 1988
Approximate string matching forms an important ingredient in many information systems. Commonly employed software methods for approximate string matching are computationally expensive, frequently making use of algorithms that compare the input string with every entry in a system database or dictionary. This paper examines the structure, implementation, and performance of a special-purpose string matching microprocessor. Details are given of a Multibus interface designed to ensure an optimal performance from the device. The design utilizes a single-board, configured as a Multibus slave, containing the Proximity processor and l/2 Mbyte of dual-ported RAM. The paper compares the performance of the dynamic programming algorithm and the Proximity processor, and highlights the speed and recall advantages of the latter.
Generalized Parallelization of String Matching Algorithms on SIMD Architecture
String matching is a classical problem in computer science. Numerous algorithms are known to solve the string matching problem such as Brute Force algorithm, KMP, Boyer Moore, various improved versions of Boyer-Moore, Bit Parallel BNDM algorithm and various others algorithms for single pattern string matching, Aho-Corasick, multiple pattern bit parallel algorithm for multiple pattern string matching. The algorithms have mainly been designed to work on a single processor called as sequential algorithms. To make the algorithms more time efficient by utilizing the processor maximum, a parallel approach the generalized text division concept of parallelization for string matching has been introduced. The parallelized approach is conceived by dividing the text and different parts of the text are worked simultaneously upon the same string matching algorithm to match the patterns. The concept is applicable to any of exact single and multiple pattern string matching algorithms. The notion of text dividing achieves parallelization on a SIMD parallel architecture. As different parts of the text are processed in parallel, special attention is required at the connection or division points for consistent and complete searching. This concept makes all string matching algorithms more time efficient in compare to the sequential algorithm. This paper presents how different string matching algorithms are implemented using the parallelization concept on different SIMD architectures like multithreaded on multi-core and GPUs. There performance comparison also shown in this paper. https://sites.google.com/site/ijcsis/
Proceedings of the 11th International Conference on Advances in Information Technology, 2020
An intrusion detection system monitors and analyzes all the incoming packets, on a given network, to detect any corresponding vulnerabilities and intrusions. It consists of four major modules: packet capturing, packet decoding, packet preprocessing and string/pattern matching. Among these, the string matching is computationally the most intensive part and a number of hardware architectures/designs have already been proposed to accelerate its performance. Consequently, an exploration of existing hardware architectures for string matching algorithms is critical. This paper identifies the most frequently used string matching algorithms and techniques, utilized for the hardware implementation. Subsequently, an exploration of various hardware architectures is provided for the identified algorithms and techniques. Finally, the implementation details of explored architectures are discussed in terms of the used device, consumed hardware resources, operational clock frequency and throughput.
Journal of Computer Science and Engineering (JCSE)
The strategy of packing several data values in a single computer word and refreshing them all in a solitary operation is referred to bit parallelism. It assumes a significant part in pattern matching because it can handle in parallel the length of pattern sizes. In this paper, an Improved Pattern Matching model (IPM) proposed, which makes searching process quicker and decreases how much memory used in processing input data. C# was used for the development of the model. With a computer word size of 64bits and pattern length ranging from 8 characters to 72 characters, the system decides how much memory is used. The developed model was evaluated and contrasted with the existing model using 64bits computer word size (cws) and the pattern length of 72 characters. The assessment showed that the IPM had minimal worth of MU contrasted with the existing model (BNDM, SBNDM, and FSBNDM). This IPM model can be embraced for improvement of the size of string data stored in computer word because o...