Calibration Techniques for Low-Power Wireless Multiband Transceiver (original) (raw)

Tradeoffs and design of an ultra low power UHF transceiver integrated in a standard digital CMOS process

Drug Discovery Today, 2000

A broad range of high-volume consumer applications require low-power, battery operated, wireless microsystems and sensors. These systems should reconcile a sufficient battery lifetime with reduced dimensions, low cost and versatility. The design of such systems highlights many tradeoffs between performances, lifetime, cost and power consumption. Also, special circuit and design techniques are needed to comply with the reduced supply voltage (down to 1 V). These considerations are illustrated by design examples taken from a transceiver chip realized in a standard 0.5 μm digital CMOS process. The chip is dedicated to a distributed sensors network and is based on a direct-conversion architecture. The circuit prototype operates in the 434 MHz ISM band and consumes only 1 mW in receive mode. It achieves a -95 dBm sensitivity for a data rate of 24 kbit/s. The transmitter section is designed for 0 dBm output power under the minimum 1 V supply, with a global efficiency higher than 15%.

CMOS Technology Dedicated to Low Power Consumption Wireless Applications

2014

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

A 0.8V, 152 μW, 433 MHz Mixer-First Receiver with a Self-Adjusted Frequency Tracking Loop

IEEE Access, 2021

This paper presents a 433 MHz low-power receiver utilizing an N-path filter technique and a self-frequency tracking mechanism. Without the front-end amplifier, the mixer-first architecture can reduce power consumption significantly. A self-adjusted frequency tracking loop (SA-FTL) adjusts local oscillator (LO) frequency to approach input RF frequency automatically, thereby enhancing conversion gain and lowering return loss. The receiver, implemented in a <inline-formula> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process, achieves a sensitivity of −80 dBm at a bit error rate (BER) of 10<sup>−3</sup> and a data rate of 10 kb/s, while consuming <inline-formula> <tex-math notation="LaTeX">$152~\mu \text{W}$ </tex-math></inline-formula> from a 0.8V voltage supply.