A Logic-Based Approach for Hardware/Software Codesign (original) (raw)

Introduction to Formal Hardware Verification

1999

Formal hardware veri cation has recently attracted considerable interest. The need for \correct" designs in safety-critical applications, coupled with the major cost associated with products delivered late, are two of the main factors behind this. In addition, as the complexity o f t h e designs increase, an ever smaller percentage of the possible behaviors of the designs will be simulated. Hence, the con dence in the designs obtained by s i m ulation is rapidly diminishing. This paper provides an introduction to the topic by describing three of the main approaches to formal hardware veri cation: theorem-proving, model checking, and symbolic simulation. We outline the underlying theory behind each approach, we illustrate the approaches by applying them to simple examples, and we discuss their strengths and weaknesses. We conclude the paper by describing current on-going work on combining the approaches to achieve m ulti-level veri cation approaches.

Design and verification languages

… of Computer Science Columbia University, New …, 2004

After a few decades of research and experimentation, registertransfer dialects of two standard languages-Verilog and VHDL-have emerged as the industry standard starting point for automatic large-scale digital integrated circuit synthesis. Writing RTL descriptions of hardware remains a largely human process and hence the clarity, precision, and ease with which such descriptions can be coded correctly has a profound impact on the quality of the final product and the speed with which the design can be created.

Formal verification in hardware design

ACM Transactions on Design Automation of Electronic Systems, 1999

In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing.There are two main aspects to the application of formal methods in a design process: the formal framework used to specify desired properties of a design and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between ω-regular languages. The verification techniques presented include model checking, automata-theoretic techniques, automated theorem proving, and approaches that integrate the above methods.In order to provide insight in...

Using formal specifications for functional validation of hardware designs

Design & Test of Computers, IEEE, 2002

Formal specifications can help resolve both ambiguity issues and correctness problems in verifying complex hardware designs. This new methodology shows how specifications can also help design productivity by automating many procedures that are now done manually. Input sequences, output assertions, and a simulation coverage metric for the design under verification are all generated directly from the specification

Formal hardware verification methods: A survey

Formal Methods in System Design, 1992

Growing advances in VLSI technology have led to an increased level of complexity in current hardware systems. Late detection of design errors typically results in higher costs due to the associated time delay as well as loss of production. Thus it is important that hardware designs be free of errors. Formal verification has become an increasingly important technique towards establishing the correctness of hardware designs. In this article we survey the research that has been done in this area, with an emphasis on more recent trends. We present a classification framework for the various methods, based on the forms of the specification, the implementation, and the proof method. This framework enables us to better highlight the relationships and interactions between seemingly different approaches.

Logic programming applied to hardware design specification and verification

ACM SIGMICRO Newsletter, 1984

This paper proposes the use of logic programming techniques in the specification and verification of hardware designs. Logic programming specifications are formal and directly executable. The advantages of executable specifications are: (1) the specification is itself a prototype of the specified system, (2) incremental development of specifications is possible, (3) behavior exhibited by the specification when executed can be used to check conformity of the specification with requirements. We discuss how Horn clause logic, which has a procedural interpretation, and predicate logic programming language, Prolog, can be used as a hardware description language to specify and verify the correctness of hardware systems. The Prolog system possesses a backtracking mechanism and a powerful pattern-matching feature which is based on unification. A novel feature of the proposed approach is that it can be used to answer interesting questions about a hardware design without resorting to simulation.

A flexible specification framework for hardware-software codesign (poster paper)

Proceedings of the conference on Design, automation and test in Europe, 2000

In this poster, we present a new specification technique for complex hardware-software systems, based on standard high-level programming languages, such as C, C++, Java, Scheme, or Ada, without extensions or semantic changes. Unlike previous approaches, the designer may choose the model of computation and the specification language that best suits her needs, while still being able to formally verify the correctness of the specification. The details of the available hardware and software resources, and the implementation of the different models of computation are encapsulated in libraries to maximize reuse in system specifications.

Linking simulation with formal verification at a higher level

IEEE Design and Test of Computers, 2004

VERIFICATION RESEARCH has primarily focused on checking the properties of algorithm-level, executable formal specifications, with less attention on verifying the conformance of complex, highly concurrent hardware designs to higher-level descriptions-a labor-and computation-intensive process based largely on software simulation that, in practice, is never entirely completed.

Embedding hardware verification within a commercial design framework

Lecture Notes in Computer Science, 1993

A methodology for verifying complex circuits is presented, based on a strong coupling of design veri cation with the hierarchical design process. This goal has been achieved by integrating MEPHISTO, a tool for semi-automated hardware veri cation, into a commercial design framework. MEPHISTO decomposes the veri cation goal by a set of hardware-speci c proof tactics and provides strategies for synthesizing pre-veri ed regular components. In case of erroneous implementations, MEPHISTO aids the designer in debugging the circuit by generating a counter model, i.e. input stimuli where speci cation and implementation behave di erently.

Combining Software and Hardware Verification Techniques

Formal Methods in System Design, 2002

Combining verification methods developed separately for software and hardware is motivated by the industry's need for a technology that would make formal verification of realistic software/hardware co-designs practical. We focus on techniques that have proved successful in each of the two domains: BDD-based symbolic model checking for hardware verification and partial order reduction for the verification of concurrent software programs. In this paper, we first suggest a modification of partial order reduction, allowing its combination with any BDD-based verification tool, and then describe a co-verification methodology developed using these techniques jointly. Our experimental results demonstrate the efficiency of this combined verification technique, and suggest that for moderate-size systems the method is ready for industrial application.