Two New Low-Power and High-Performance Full Adders (original) (raw)
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Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
Journal of Computers, 2008
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP. We have performed simulations using HSPICE in a 90 nanometer (nm) standard CMOS technology at room temperature; with supply voltage variation from 0.65v to 1.5v with 0.05v steps.
Two new low-power Full Adders based on majority-not gates
Microelectronics Journal, 2009
Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-ofthe-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18 mm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).
Microelectronics …, 2009
A new low-power full-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gates such as NOR, NAND and MAJORITY-NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18 mm and 90 nm CMOS process technologies. The proposed fulladder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially whenever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively.
A novel high-performance CMOS 1-bit full-adder cell
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 2000
A novel 16-transistor CMOS 1-bit full-adder cell is proposed. It uses the low-power designs of the XOR and XNOR gates [1], pass transistors, and transmission gates. The cell offers higher speed and lower power consumption than standard implementations of the 1-bit full-adder cell. Eliminating an inverter from the critical path accounts for its high speed, while reducing the number and magnitude of the cell capacitances, in addition to eliminating the short circuit power component, account for its low power consumption. Simulation results comparing the proposed cell to the standard implementations show its superiority. Different circuit structures and input patterns are used for simulation. Energy savings up to 30% are achieved.
Implementation of Novel Ultra-Low Power and High-Speed 1-Bit Full Adder Cell
This paper presents a novel ultra-low power and high speed 1-bit Full-Adder, which is designed only based on pass transistor logic. The main advantages of this design are very low propagation delay and ultra-low consumption power, which lead to achieve lower PDP and EDP than that of other. Intensive HSPICE simulation indicates that the new Full-Adder consumes around 70% less power than 14T Adder, moreover its EDP 83% is lesser than 28T Full-Adder. We have compared some of the most popular Full-Adders like 28T, CPL, SS16T, 10T, and 14T to the proposed Full-Adder. Simulation has been carried out by HSPICE in 0.18µm technology at 1.8V supply voltage.
Modified Low-Power Hybrid 1-Bit Full Adder
2018
The usage of digital devices is increasing rapidly and they became essential part of everyone’s life. Digital devices can be designed according to their application and most of them are realized using arithmetic processor which consists of several operations like addition, subtraction, multiplication, etc., all of them can be implemented using full adder as the basic building block. As full adder plays a major role in digital devices we need to design a low-power full adder such that the devices can operate at lower power consumption and has longer battery life. In this research work, a hybrid low-power 1-bit full adder was designed using CMOS logic, pass transistor, and transmission gate logic with 14 transistor. The design was simulated using HSPICE tools in 90 nm technology with supply voltage of 1.2 V. Performance parameters, such as power, delay, and power delay product were compared with the existing designs, such as C-CMOS Full Adder, Mirror adder, hybrid pass-logic with stat...
Design and Performance Analysis of High Speed Low Power 1 bit Full Adder
2017
In this Paper, design of high speed, low power 1-bit full adder using both logic gates and complementary metal oxide semiconductor (CMOS) logic is implemented. The main purpose behind designing this full adder is to reduce power and delay of standard implementation by replacing OR gate with XOR gate for output carry generation. The design proposed was first implemented using CEDAR logic tool and then with cadence virtuoso tool in 180nm technology. The simulation was carried out at 1.8V supply with length and width of each transistor taken as 0.18 μm and 2 μm. Performance parameters such as power, speed and design of existing full adder is compared with the proposed design. In comparison with the standard implementation of full adder, the present implementation was found to offer significant improvement in terms of power and speed.
Performance analysis of low-power 1-bit CMOS full adder cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002
A performance analysis of 1-bit full-adder cell is presented. The adder cell is anatomized into smaller modules. The modules are studied and evaluated extensively. Several designs of each of them are developed, prototyped, simulated and analyzed. Twenty different 1-bit full-adder cells are constructed (most of them are novel circuits) by connecting combinations of different designs of these modules. Each of these cells exhibits different power consumption, speed, area, and driving capability figures. Two realistic circuit structures that include adder cells are used for simulation. A library of full-adder cells is developed and presented to the circuit designers to pick the full-adder cell that satisfies their specific applications.
A novel low-power full-adder cell for low voltage
Integration, the VLSI Journal, 2009
This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the timeconsuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-mm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.
Low-voltage low-power CMOS full adder
Circuits, Devices and Systems, IEE …, 2001
Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many innovative designs for basic logic functions using pass transistors and transmission gates have appeared in the literature recently. These designs relied on the intuition and cleverness of the designers, without involving formal design procedures. Hence, a formal design procedure for realising a minimal transistor CMOS pass network XOR-XNOR cell, that is fully compensated for threshold voltage drop in MOS transistors, is presented. This new cell can reliably operate within certain bounds when the power supply voltage is scaled down, as long as due consideration is given to the sizing of the MOS transistors during the initial design step. A low transistor count full adder cell using the new XOR-XNOR cell is also presented.