Concurrent Placement and Routing in the Design of Integrated Circuits (original) (raw)
Complexity
When used in conjunction with the current floorplan and the optimization technique in circuit design engineering, this research allows for the evaluation of design parameters that can be used to reduce congestion during integrated circuit fabrication. Testing the multiple alternative consequences of IC design will be extremely beneficial in this situation, as will be demonstrated further below. If the importance of placement and routing congestion concerns is underappreciated, the IC implementation may experience significant nonlinear problems throughout the process as a result of the underappreciation of placement and routing congestion concerns. The use of standard optimization techniques in integrated circuit design is not the most effective strategy when it comes to precisely estimating nonlinear aspects in the design of integrated circuits. To this end, advanced tools such as Xilinx VIVADO and the ICC2 have been developed, in addition to the ICC1 and VIRTUOSO, to explore for co...
Optimization of an Integrated Circuit Placement Algorithm in a Parallel Environment
This paper presents an implementation of GORDIAN [1], a method for Global Placement of standard-cell based circuit designs, incorporating a number of algorithmic optimizations and parallelization in order to reduce the total runtime and memory requirements and improve the solution quality. Experimental results are presented, comparing GODRIAN to other state-of-the-art academic placers, which highlight the improved execution speed and the limited memory footprint which are GORDIAN’s main advantages. Thus, GORDIAN runs faster than any other proven placer while still producing acceptable results, enabling million-cell designs to be placed within a few minutes.
Timing-driven via placement heuristics for three-dimensional ICs
Integration, the VLSI Journal, 2008
The dependence of the interconnect delay on the interplane via location in three-dimensional (3-D) ICs is investigated in this paper. The delay of these interconnects can be significantly decreased by optimally placing the interplane vias. The via locations that minimize the propagation delay of two-terminal interconnects consisting of multiple interplane vias under the distributed Elmore delay model are determined. For interconnect trees, the interplane via locations that minimize the summation of the weighted delay of the sinks of the tree are also determined. For these interconnect structures, the interplane via locations are obtained both through geometric programming and near-optimal heuristics. Placement constraints are imposed such that the path is negligibly affected. The proposed heuristics are used to implement efficient algorithms that exhibit lower computational times as compared to general optimization solvers with negligible loss of optimality. Various interplane via placement scenarios are considered. Simulation results indicate delay improvements for relatively short point-to-point interconnects of up to 32% with optimally placed interplane vias. For interconnect trees, the maximum improvement in delay for optimally placed interplane vias is 19%. The proposed algorithms can be integrated into a design flow for 3-D circuits to enhance placement and routing where timing is a primary design criterion. r
A performance-driven placement tool for analog integrated circuits
IEEE Journal of Solid-State Circuits, 1995
This paper presents a new approach toward performance-driven placement of analog integrated circuits. The freedom in placing the devices is used to control the layout-induced performance degradation within the margins imposed by the designer's specifications. This guarantees that the resulting layout will meet all specifications by construction.
Review Paper on Placement Algorithms
IJEER, 2016
Placement is a step considered after floor planning in FPGA flow in ASIC. It defines the location of logic cells within functional blocks and to minimize the routing length. We adjust the logic cells in this way so that minimum interconnect length, area and density are used. In this paper we will discuss some of methods of placement of logic cells.
Malaysian Journal of …, 2009
In this paper, we describe a routing optimization algorithm based on grid-graphs for application in a deep-submicron VLSI layout design. The proposed algorithm, named S-RABILA (for Simultaneous Routing and Buffer Insertion with Look-Ahead), constructs a maze routing path, simultaneously with buffer insertion and wire sizing, taking into account wire and buffer obstacles, such that the interconnect delay from source to sink is minimized. In current nanometer VLSI layout design, the interconnect delay has become the dominant factor affecting system performance. Research has shown that routing algorithms, which include simultaneous buffer insertion and wire-sizing, have been proven to be very effective in solving the timing optimization problem in VLSI interconnect design. A key contribution of this work is a novel look-ahead scheme applied to speed up the runtime of the algorithm, and aids in finding the exact solution. Hence, the algorithm is accurate, fast, scalable with problem size, and can handle large routing graphs. Experimental results show the effectiveness of the look-ahead scheme and indicate that S-RABILA provides significant performance improvements over similar existing VLSI routing algorithms.
An analytic net weighting approach for performance optimization in circuit placement
We propose an efficient circuit placement approach based on analytic net weighting controls for nonlinear performance constraints. We justify the popular net weighting heuristic by first showing that an appropriate net weighting is a natural result of the Kuhn-Tucker conditions of circuit placement optimization subject to the performance constraints. We further give a quantitative analysis of the effect of net weighting to wire length change. An effective net weighting control algorithm has been implemented and applied to real chip designs. The results are very promising. A performance-optimized result can be achieved in 13.2 seconds for a chip with 1,403 circuits. An experimental CMOS chip with 45,296 circuits has a complete placement result in 40 minutes while the wire length measure is 20.3 percent better than a simulated annealing approach.
Performance-driven constructive placement
27th ACM/IEEE Design Automation Conference
A new approach to the performance-driven placement based on a window concept is presented. We fist convert timing constraints to geometric shapes using the defined windows. A window represents a region in which all the modules along a given path can be placed without degrading the circuit performance. Then a constructive placement process uses the window information to select an unplaced module, and to find an appropriate position for the module. This approach represents a unified way to consider both timing and geometric constraints during the placement process. The experimental results show that the improvement of circuit perEormance can be achieved by the sufficient use of the window information.
Standard cell placement is a NP complete open problem. The main objectives of a placement algorithm are to minimize chip area and the total wire length of all the nets. Due to interconnect dominance, Deep Sub Micron VLSI design flow does not converge leading to iterations between synthesis and layout steps. We present a new heuristic placement algorithm called Sankeerna, which tightly couples synthesis and routing and produces compact routable designs with minimum area and delay. We tested Sankeerna on several benchmarks using 0.13 micron, 8 metal layer, standard cell technology library. There is an average improvement of 46.2% in delay, 8.8% in area and 114.4% in wire length when compared to existing placement algorithms. In this paper, we described the design and implementation of Sankeerna algorithm and its performance is illustrated through a worked out example.
ACM Transactions on Design Automation of Electronic Systems, 2005
Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50% to 150% away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technology-generation advancements. The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and p...