Planning and managing top-down, concurrent VLSI design processes (original) (raw)

A methodology and design tools to support system-level VLSI design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1995

System-level design involves making major design decisions without having accurate information on the eventual system characteristics. This paper presents a novel constraintdriven methodology to support system-level design. The software assists a designer or a tool in partitioning behavioral specifications onto multiple VLSI chips and in system design while satisfying hard constraints such as individual chip areas, chip pin counts, system throughput (inverse of system initiation interval) and system latency (delay). The software uses search and estimation techniques to perform comprehensive design-space exploration and evaluates partitions supplied by the user or by other synthesis software. The technique determines what design characteristics each partition must possess in order to satisfy area, pin, throughput and latency constraints. The paper also includes results of extensive experiments with the methodology.

ULYSSES—a knowledge-based VLSI design environment

Artificial Intelligence in Engineering, 1987

Ulysses is a VLSI computer-aided design (CAD) environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment employs artificial intelligence techniques, functions as an interactive expert system, and interprets descriptions of design tasks encoded in the scripts language. The architecture of Ulysses is described in detail. Ulysses has been successfully used to perform a VLSI chip floor planning and layout task and has produced an example chip.

A knowledge-based approach to VLSI-design in an open CAD-environment

Microprocessing and Microprogramming, 1989

A knowledge-based approach is suggested to assist a designer in the increasingly complex task of generating VLSI-chips from abstract, high-level specifications of the system. The complexity of designing VLSI-circuits has reached a level where computer-based assistance has become indispensable. Not all of the design tasks allow for algorithmic solutions. AI techniques can be used, in order to support the designer with computer-aided tools for tasks not suited for algorithmic approaches. The approach described in this paper is based upon the underlying characteristics of VLSI design processes in general, comprising all stages of the design. A universal model is presented, accompanied with a recording method for the acquisition of design knowledge -strategic and task-specific -in terms of the design actions involved and their effects on the design itself. This method is illustrated by a simple design example: the implementation of the logical EXOR-component. Finally suggestions are made for obtaining a universally usable architecture of a knowledge-based system for VLSI-design.

Technology transfer between VLSI design and software engineering: CAD tools and design methodologies

Proceedings of the IEEE, 1986

Recent research on the explicit transfer of technology used in computer-aided design (CAD) tools and design methodologies is reported. First, several examples are given of applications of these technologies to software engineering. Then, three research projects are described which focused on applying software engineering principles to the VLSl design process. They are: a methodology, language, and assessment tool for multilevel mixed-mode VLSl designs; a research project that explored the potential for transfer of software design methodologies for managing VLSI design complexity; and a specification technique for "modules" in a VLSl design that localizes the impact of changes to the design. Next, a CAD tool and design methodology are described which consider the design of software and hardware together, and apply common techniques to both. Finally, some observations are made on the appropriateness of technology transfer between VLSI design and software engineering.

The Design of VLSI Design Methods

The Mead-Conway VLSI design and implementation methodologies were deliberately generated to be simple and accessible, and yet have wide coverage and efficiency in application. An overview is given of the methods used to "design the design methodology." We sketch the results and the status of these methods, and of the associated infrastructure of university courses, computer network communities, silicon implementation systems, and silicon foundries in the United States.

A formal basis for design process planning and management

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1996

We have reached the point where we need to move beyond the development of CAD tools that only aid designers in solving specific synthesis, analysis, and/or optimization design problems but also aid designers in planning and managing the increasingly complex design process itself. In order to achieve this goal we need to be able to formally characterize and represent the fundamental intentions, strategies, and mechanisms employed during the design process. In other words, we need to be able to formalize the content or the semantics of design rather than simply allowing this information to remain hidden in the syntactical idiosyncrasies of the design "form." Observe that through the realization of such a syntactically transparent and semantically rich design formalism, it becomes possible to articulate the essential concepts of design and model both the design artifacts and the process of design across multiple design disciplines, in a coherent and precise way. In fact we will show that a design formalism with the above characteristics is immediately useful in guiding the development of general purpose, highly effective design process planning and managements meta-tools. Because such meta-tools are capable of capturing the fundamental strategies for controlling complexity embed in traditional design methodologies, and by intelligently making use of such strategies throughout the design process, they allow for the realization of a new generation of powerful CAD environments.

A Hierarchical Planning Tool for Custom VLSI Layout

Computer Sciences Forum (Honeywell), 1984

This article describes a chip planning tool called SPIDER (Spatial Planning and Interactive Environment for Research) for planning the layout of custom VLSI circuits. Some of the algorithms used are technology independent while others are specific to ISL (integrated Schottky Logic) technology. Thus, in the case of ISL, a close match between the layout tool, the design style and the technology is possible. The ISL dependent portions of SPIDER are insulated from the technology independent portions. The planning tool provides estimates of the chip area, the interconnection wiring space between the function blocks and a floor plan indicating the relative placement of the function blocks. An overview of SPIDER which outlines the overall philosophy and the various tasks in chip planning, is given. Some experiments in chip planning with SPIDER are then described. Finally extensions to the scope of the planning tool are discussed. (With Raja S. Ramnarayan, PhD)

A methodology for custom VLSI layout

IEEE Transactions on Automatic Control, 1983

In this paper, we present a new methodology for custom VLSI layout which aims at a low turnaround time and a high quality of design. VLSI circuits are highly complex, and to speed up the design process we exploit the hierarchical structure of a design, splitting the problem domain into several levels. The process of layout at each level is divided into steps such as placement of rectangular blocks, determining block dimensions, determining interconnection paths, etc. In order to obtain high quality designs, we have systematically analyzed the relationship among the parameters being computed at various steps and have accordingly organized the flow of data and control through these steps. There are two novel features in our scheme. First, we do not follow the usual pure top-down or pure bottom-up approach, so as to take into account the infl.uence of design decisions at the higher levels on design decisions made at the lower levels, as well as vice versa. For example, we determine the geomehy of a block taking into consideration the context in which it is placed, as well as the geometries of the lower level blocks it encloses. Second, we perform a look-ahead operation when the values of some. parameters are needed before they are actually deterministically computable by the process. For example, at the ,time of placement, the area required for routing is estimated statistically (before doing the actual routing) so that a more routable placement can be obtained, thereby avoiding some unnecessary iterations.

A structural representation for VLSI design

Design Automation Conference, 1988

This paper presents a data structure for representing the structure of VLSI circuits and basic operations for manipulating this data structure. Its features include conceptual integrity, rich expressive power, and high extensibility. It forms the nucleus of a design analysis and synthesis system which has been used to design several major chips.

Harnessing VLSI System Design with EDA Tools

2012

This chapter is meant to be a short introduction to the Electronic Design Automation (EDA) paradigm. The last decade has witnessed phenomenal growth in the number of R&D groups, corporate players, universities and research laboratories working in this exciting area up-and-coming as the hub of interdisciplinary activity. Increasing design complexities owing to the "more than Moore" phenomenon, added expected functionalities, shrinking design cycle and time to market window, more software centric designs are all the crucial factors forcing the EDA progression in diversified directions more than ever before. The intent of this chapter is also to make the reader familiar with the very rationale of the book, its organization and to set the basic foundations of its remaining chapters which exploit various flavors of different EDA tools to build live case studies of increasing complexities. 1.2 Prologue In the era of technology shrinkage of the order of ~0.7 per generation with 2× more functions per generations and declining cost of the functions by the same order; the Electronic Design Automation tools are at the forefront of the Very Large Scale Integration (VLSI) design. Electronic Design Automation (EDA) is one of the key enablers of the semiconductor industry [1]. No chip is designed without EDA. Conversely, semiconductors drive EDA technology [2]. These EDA tools are now progressively more required to address the microscopic and macroscopic design issues. The former includes design concerns such as ever-increasing speed, more demand towards reduction in power supply and power dissipation, noise, crosstalk, interconnects and overall reliability aspects. While the later comprises of productivity challenges with the shrinking time to market window, different levels of abstractions Chapter 1