A 10bit 1MHZ SAR ADC for Automobile Electronics MCU with Rail-to-Rail Input Swing (original) (raw)
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Design and Implementation of 10 Bit, 2MS/s Split SAR ADC Using 0.18um CMOS Technology
International Journal of VLSI Design & Communication Systems, 2015
This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter (DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is 96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimized architecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy of the components, which improves the performance of SAR ADC. Comparator constructed from resistances, capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.
A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology
2017
In this paper, a new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on capacitor merged technique is presented. The main goal of the proposed idea is to achieve high-resolution and high-speed SAR ADC, simultaneously. It is noteworthy that, exerting the suggested method, the total capacitance and the ratio of the MSB and LSB capacitors are decreased; as a result, the speed and accuracy of the ADC are increased reliably. Therefore, applying the proposed idea, it is reliable that to attain a 12-bit resolution ADC at 76MS/s sampling rate. Furthermore, the power consumption of the proposed ADC is 694µW with the power supply of 1.8 volts correspondingly. The proposed postlayout SAR ADC structure is simulated in all process corner conditions and different temperatures of-50℃ to +50℃, and performed using the HSPICE BSIM3 model of a 0.18µm CMOS technology.
A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application
Electronics, 2020
A design of low-power 10-bit 1 MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC) is presented in this paper. To improve the linearity of the digital-to-analog converter (DAC) and energy efficiency, a common mode-based monotonic charge recovery (CMMC) switching technique is proposed. The proposed switching technique consumes only 63.75 CVREF2 switching energy, which is far less as compared to the conventional switching technique without dividing or adding additional switches. In addition, bootstrap switching is implemented to ensure enhanced linearity. To reduce the power consumption from the comparator, a dynamic latch comparator with a self-comparator clock generation circuit is implemented. The proposed prototype of the SAR ADC is implemented in a 55 nm CMOS (complementary metal-oxide-semiconductor) process. The proposed architecture achieves a figure of merit (FOM) of 17.4 fJ/conversion, signal-to-noise distortion ratio (SNDR) of 60.39 dB, ...
International Journal of Circuits, Systems and Signal Processing
The proposed work presents a High speed 14-bit 125MS/s successive-approximation-register asynchronous analog-to-digital-converter (SAR-ADC). A novel-based Dual-Split-Array-Three-Section (DSATS) capacitor DAC (DSATS-CDAC) is employed to increase the linearity and energy efficiency of the digital-to-analog converter (DAC), additional advantage of this work is that, the area is reduced by 59.76% of conventional design. The proposed switching technique of the (DSATS-CDAC) consumes less switching energy. Additionally, bootstrap switching is employed to ensure improved linearity and reduced power consumption.in order to enhance the speed of operation and increase the precision a preamplifier latch based comparator is implemented with the delay of 250ps. The proposed SAR-ADC prototype is implemented in a 90nm CMOS process and consumes a power of 42.8mW at 1V operating supply. The proposed design achieves a figure of merit (FOM) of 37.43 fJ/conversion-step, signal-to-noise-ratio (SNR) of 81...
A low power 12-bit 1MSps SAR ADC with capacitor array network
This paper proposes a low power 12-bit 1MSps SAR ADC (Successive Approximation Register Analog-to-Digital Converter) with capacitor array network for SoC (System-on-Chip). The proposed circuit is designed using Magnachip/SK Hynix 0.18 μm CMOS 1Poly-6Metal process, and it is powered by 1.5 supply voltage. The proposed circuit in this paper showed high SNDR (Signal-to-Noise Distortion Ratio) of 71.18dB, and excellent ENOB (effective bit number ofbits) of 11.53-bit as compared to conventional research results. The designed circuit also showed very low power consumption of 1.95mW
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
This paper presents a low-power 10-bit 50-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a monotonic capacitor switching procedure. Compared to converters that use the conventional procedure, the average switching energy and total capacitance are reduced by about 81% and 50%, respectively. In the switching procedure, the input common-mode voltage gradually converges to ground. An improved comparator diminishes the signal-dependent offset caused by the input common-mode voltage variation. The prototype was fabricated using 0.13-m 1P8M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 57.0 dB and consumes 0.826 mW, resulting in a figure of merit (FOM) of 29 fJ/conversion-step. The ADC core occupies an active area of only 195 265 m 2 .
A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS
Analog Integrated Circuits and Signal Processing, 2016
Abstract In sensor applications, low-power and moderate-high resolution analog-to-digital converters (ADCs) are needed to convert the analog front-end signal output. Such systems are often multi-channel and require analog multiplexing. In these cases, even when high resolutions are required, continuous time \varDelta \varSigma ΔΣ ADCs can’t be adopted, and an efficient data-conversion must be achieved relying on different topologies, typically successive approximation-register (SAR) ADCs. Since these systems are often implemented in CMOS processes like 250- and 350-nm CMOS to benefit from a large supply voltage, the SAR ADC design is challenging due to the technology mismatch and to the limited number of metals available to optimize the layout. This paper presents a SAR ADC implemented in 350-nm CMOS technology with a physical resolution of 14 bits using a binary weighted with attenuation capacitor array. The proposed converter exploits a semi-custom and isotropic unit capacitance with ground shield to avoid proximity effects and parasitic capacitances across its terminals, an optimized capacitive array layout insensitive to both linear and radial oxide gradients, and an efficient calibration algorithm to compensate the parasitic capacitances that worsen the converter linearity. At 1.8-V supply and 100-kSps sampling frequency, the proposed ADC achieves an SNDR of 70.7 dB, an SFDR of 81.8 dB, an ENoB of 11.45 and a power consumption of 43.4μW, corresponding to a figure-of-merit (FoM) of 155 fJ/conv.step. To the best of our knowledge, this figure is the best among SAR converters implemented in 350-nm or less scaled technologies, and in-line with other ADCs featuring an SNDR larger than 70 dB.
A sub-1 Volt 10-bit supply boosted SAR ADC design in standard CMOS
Analog Integrated Circuits and Signal Processing, 2011
This paper presents a new very low-power, low-voltage successive approximation analog to digital converter (SAR ADC) design based on supply boosting technique. The supply boosting technique (SBT) and supply boosted (SB) circuits including level shifter, comparator, and supporting electronics are described. Supply boosting provides wide input common mode range and sub-1 Volt operation for the circuits designed in standard CMOS processes that have only high-V t MOSFETs. A 10bit supply boosted SAR ADC was designed and fabricated in a standard 0.5 lm, 5 V, 2P3M, CMOS process in which threshold voltages of NMOS and PMOS devices are ?0.8 and -0.9 V, respectively. Fabricated SB-SAR ADC achieves effective number of bits (ENOB) of 8.04, power consumption of 147 nW with sampling rate of 1.0 KS/s on 1 Volt supply. Measured figure of merit (FOM) was 280 fJ/ conversion-step. Proposed supply boosting technique improves input common mode range of both SB comparator and SAR ADC, allows sub-1 Volt operation when threshold voltages are in the order of the supply voltage, and achieves low energy operation. Thus, SBT is suitable for mixed-signal circuit designed for energy limited applications and systems in where supply voltage is in the order of threshold voltages of the process.
A 1.2V 8 Bit Sar Analog to Digital Converter in 90NM Cmos
Successive approximation register (SAR) analog to digital converters are widely utilized for low speed and low power applications. This paper shows a configuration of a 8 bit SAR ADC which uses monotonic capacitor switching strategy. This switching plan lessens the total capacitance in the DAC circuit which by implication prompts reduction in power consumption. Dynamic latch comparator with stack approach is utilized among the key building modules of SAR ADC, the use of this comparator lessens the leakage current in the circuit. The designed 8 bit SAR ADC is executed by utilizing 90nm CMOS technology and works at supply voltage of 1.2V. The planned SAR analog to digital converter consumes 93.01µW power. Keywords: Analog to digital converter (ADC), capacitive network, digital to analog converter (DAC), Successive approximation register(SAR)
Analog Integrated Circuits and Signal Processing, 2019
Successive-approximation-register (SAR) ADC has gained popularity owing to its low power consumption in the growing field of ADC development. This work describes such a structure through the use of a novel low offset comparator thereby reducing the non-linearity performance along with significant improvement in energy-delay metric. A high speed control circuitry is introduced to improve the overall frequency of operation of SAR-ADC minimizing its speed limitation. Capacitive based digital-to-analog converter is used that switches in alternate cycles to reduce the static power dissipation. The ADC architecture is designed in 45-nm CMOS technology at layout of 0:0139 mm 2. The extracted results show that the proposed design is a reliable framework to ascertain the effectiveness of SAR-ADC with a faster performance. The results demonstrate an improvement of 47.75% in figure-of-merit. SNDR and SFDR are found to be 57.2 dB and 61.4 dB respectively at input frequency of 10 MHz. The sampling frequency is taken as 1 GHz with a power supply of 1 V.