Performance Investigation of a full adder using CNTFET Technology (original) (raw)
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A low-power high speed full adder cell using carbon nanotube field effect transistors
The Indonesian Journal of Electrical Engineering and Computer Science (IJEECS), 2023
The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.
An applicable high-efficient CNTFET-based full adder cell for practical environments
Full adder is among the most practical logic blocks. It is the main arithmetical component of all digital systems. This paper presents the novel design of a high-speed and high-efficient full adder cell which is on the basis of low-complex passtransistor logic. Using carbon nanotube field effect transistors, formation of transmission gates are not required and the usage of extra transistors is avoided. It benefits from ultra high computational speed which makes it ideal for high-speed and high-frequency applications. It could be employed in portable devices as it consumes very low power. It has also the advantage of working reliably in spite of fabrication imperfections. Simulations are carried out using Synopsys HSPICE in a realistic test bench and other various strict conditions. Simulation results demonstrate higher efficiency with respect to other conventional and state-of-the-art CNTFET and MOSFET implementations.
Analysis of FinFET and CNTFET based Hybrid CMOS Full Adder Circuit
IRJET, 2022
In the world of IC, the technology scales down to 32nmor below and CMOS has lost its recommendation during scaling beyond 32nm due to high power consumption and high leakage current. Scaling triggers Short Channel Effects that can be hard to conquer. So, FinFET is used because it reduces the shortchannel effects. FinFET can be used in the nanometre range. CNTFET is one of the replacements for present CMOS technology because it can provide a stronger control over the thin Si body and reduces the short channel effects. As the full adder is one of the most promising units of the ALU because it reduces speed and power consumption. The logic style used for implementation is a Hybrid CMOS (HC) Full adder which consumes fewer transistors and reduces power. Both technologies (FinFET and CNTFET) reduces short channel effects and can be used in nanometre technologies. In this paper, the main objective is to find out the analysis of the best efficient devices between FinFET and CNTFET based on the Hybrid CMOS Full Adder circuit. Here, these are proposed FinFET based Hybrid CMOS Full Adder and CNTFET based Hybrid CMOS Full Adder. These new hybrid adder is having only 10 transistors. The proposed full adder is a CNTFET and FinFET based design implemented using Synopsys tools in 32nm, 16nm, 10nm technology and calculates Power consumption, delay, and Power Delay Product (PDP) are investigated and showed with better result comparison
Energy Efficient CNTFET Based Full Adder Using Hybrid Logic
—Full Adder is the basic element for arithmetic operations used in Very Large Scale Integrated (VLSI) circuits, therefore, optimization of 1-bit full adder cell improves the overall performance of electronic devices. Due to unique mechanical and electrical characteristics, carbon nanotube field effect transistors (CNTFET) are found to be the most suitable alternative for metal oxide field effect transistor (MOSFET). CNTFET transistor utilizes carbon nanotube (CNT) in the channel region. In this paper, high speed, low power and reduced transistor count full adder cell using CNTFET 32nm technology is presented. Two input full swing XOR gate is designed using 4 transistors which is further used to generate Sum and Carry output signals with the help of Gate-Diffusion-Input (GDI) Technique thus reducing the number of transistors involved. Proposed design simulated in Cadence Virtuoso with 32nm CNTFET technology and results is better design as compared to existing circuits in terms of Power, Delay, Power-Delay-Product (PDP), Energy Consumption and Energy-Delay-Product (EDP).
Performance Study of 12-CNTFET and GDI CNTFET based Full Adder in HSPICE
This manuscript reports and analyzes 12-CNTFET and GDI CNTFET based full adder implementation at 32 nm level. As figures of merit, stability, power dissipation and Power Delay Product (PDP) are considered for the best overall performance. Intensive HSPICE simulations have been performed to investigate the distribution of the power and delay of the CNTFET-based full adders. Both circuit has noticeable reduction in short current power consumption but in terms of comparison GDI CNTFET shows better performance in both power consumption and Power Delay Product (PDP) variations. The CNTFET-based One bit Full Adder cell demonstrates that it tolerates the PVT (Process, Voltage, and Temperature) variations significantly better than its CMOS counterpart.
Design and Analysis of a New Carbon Nanotube Full Adder Cell
Journal of Nanomaterials, 2011
A novel full adder circuit is presented. The main aim is to reduce power delay product (PDP) in the presented full adder cell. A new method is used in order to design a full-swing full adder cell with low number of transistors. The proposed full adder is implemented in MOSFET-like carbon nanotube technology and the layout is provided based on standard 32 nm technology from MOSIS. The simulation results using HSPICE show that there are substantial improvements in both power and performance of the proposed circuit compared to the latest designs. In addition, the proposed circuit has been implemented in conventional 32 nm process to compare the benefits of using MOSFET-like carbon nanotubes in arithmetic circuits over conventional CMOS technology. The proposed circuit can be applied in very high performance and ultra-low-power applications.
Designing High-Speed, Low-Power Full Adder Cells Based on Carbon Nanotube Technology
International Journal of VLSI Design & Communication Systems, 2014
This article presents novel high speed and low power full adder cells based on carbon nanotube field effect transistor (CNFET). Four full adder cells are proposed in this article. First one (named CN9P4G) and second one (CN9P8GBUFF) utilizes 13 and 17 CNFETs respectively. Third design that we named CN10PFS uses only 10 transistors and is full swing. Finally, CN8P10G uses 18 transistors and divided into two modules, causing Sum and Cout signals are produced in a parallel manner. All inputs have been used straight, without inverting. These designs also used the special feature of CNFET that is controlling the threshold voltage by adjusting the diameters of CNFETs to achieve the best performance and right voltage levels. All simulation performed using Synopsys HSPICE software and the proposed designs are compared to other classical and modern CMOS and CNFET-based full adder cells in terms of delay, power consumption and power delay product.
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs). Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer technology in Different values of temperature and VDD.
Design of an Efficient Current Mode Full-Adder Applying Carbon Nanotube Technology
International Journal of Modern Education and Computer Science
In this article a new design of a current mode full-adder is proposed through the field effect transistors based on carbon nanotubes. The outperformance of the current mode full-adder constructed by CNTFET compared to that of constructed by CMOS is observable in the simulation and comparisons. This circuit operates based on triple input majority function. The simulation is run by HSPICE software according to the model proposed in Stanford University for CNTFETs at 0.65 V power supply voltage. The proposed circuit outperforms compared to the previous current mode full-adders in terms of speed, accuracy and PDP.
A low-voltage and energy-efficient full adder cell based on carbon nanotube technology
2010
Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT (Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET (Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP (Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages. Citation: Keivan Navi, Rabe'e Sharifi Rad, Mohammad Hossein Moaiyeri and Amir Momeni, "A low-voltage and energy-efficient full adder cell based on carbon nanotube technology", Nano-Micro Lett. 2, 114-120 (2010). doi:10.5101/ nml.v2i2.p114-120 Scaling down the feature size of MOSFET devices in nanometer, leads to serious challenges, such as short channel effects, very high leakage power consumption and large parametric variations. Due to these limitations researchers become eager to work toward new emerging technologies such as Quantum Automata (QCA) [1], Nanowire transistors [2] and Carbon Nanotube Field Effect Transistors (CNFET) [3]. By the mentioned problems of nanoscale CMOS technology, which makes it unsuitable for low-power and low-voltage applications in the near future, these nano-devices could replace the conventional silicon MOSFET in the time to come. However, due to the similarities between the infrastructure and functionality of the conventional MOSFET devices with CNFETs and also because of the ballistic operation of CNFETs, it could be more promising and achievable, compared to other nano-devices. Recently some efforts have been done for designing circuits based on CNFET such as multiple valued logic circuits [4,5], arithmetic circuits [6] and so on, taking