Petri net modeling of gate and interconnect delays for power estimation (original) (raw)
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Power estimation of sequential circuits using hierarchical colored hardware Petri net modeling
Proceedings of the International Symposium on Low Power Electronics and Design, 2002
A Hierarchical Colored Hardware Petri net (HCHPN) based model was proposed in [8] for estimating switching activity in combinational circuits. In this paper, we model sequential circuits as HCHPNs incorporating real delays for both gates and interconnects. Thus, the given sequential circuit is first modeled as a HCHPN and simulated for switching activity estimation in the petri net domain which leads to better accuracy and faster simulation. Experimental results for ISCAS'89 benchmark circuits show that the proposed HCHPN model yields accuracy on an average within 4.4% of that of PowerMill. The per-pattern simulation time for HCHPNs is about 2.4 times lesser than that of PowerMill.
A real delay switching activity simulator based on Petri net modeling
Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design, 2002
Switching activity estimation is an important step in power estimation of digital VLSI circuits. While simulation yields accurate results, it is time consuming. In this paper, we propose a new technique based on Petri nets for real-delay switching activity estimation that yields the same accuracy as simulation, but is significantly faster in computation. We introduce a new type of Petri net called Hierarchical Colored Hardware Petri Net (HCHP-Net). The gate-level circuit is first transformed into a directed acyclic graph called, GSDAG, in which both the gates as well as the signals correspond to the nodes in the graph. The GSDAG is then mapped onto a corresponding HCHP-Net which is then simulated using a Petri net simulator. Experimental results for ISCAS '85 circuits are presented. The method replicates exactly the switching activity results for real-delay models produced by HSPICE and PowerMill. However, the perpattern simulation time is about 51 times faster than the Synopsys PowerMill and 8900 times faster than the Avanti HSPICE.
Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model
Journal of Advanced Research, 2015
ABSTRACT Dynamic power estimation is essential in designing VLSI circuits where many parameters are involved but the only circuit parameter that is related to the circuit operation is the nodes’ toggle rate. This paper discusses a deterministic and fast method to estimate the dynamic power consumption for CMOS combinational logic circuits using gate-level descriptions based on the Logic Pictures concept to obtain the circuit nodes’ toggle rate. The delay model for the logic gates is the real-delay model. To validate the results, the method is applied to several circuits and compared against exhaustive, as well as Monte Carlo, simulations. The proposed technique was shown to save up to 96% processing time compared to exhaustive simulation.
Logic Picture-Based Dynamic Power Estimation for Unit Gate-Delay Model CMOS Circuits
Circuits and Systems, 2013
In this research, a fast methodology to calculate the exact value of the average dynamic power consumption for CMOS combinational logic circuits is developed. The delay model used is the unit-delay model where all gates have the same propagation delay. The main advantages of this method over other techniques are its accuracy, as it is deterministic and it requires less computational effort compared to exhaustive simulation approaches. The methodology uses the Logic Pictures concept for obtaining the nodes' toggle rates. The proposed method is applied to well-known circuits and the results are compared to exhaustive simulation and Monte Carlo simulation methods.
1999
This paper presents a efficient approach for the estimation of signal activity figures based on a gate level description of a digital circuit. Exploiting an event oriented simulation system a methodology for calculating very accurate power estimates for digital circuits is presented. A calibration scheme for characterizing the power dissipation of logic gates based on a few key parameters will be outlined. The proposed method proves that the use of an event oriented simulation system calibrated with these gate specific parameters allows power estimations which are comparable to transistor level (SPICE) simulation accuracy. This is essential for the analysis of large circuits, because the proposed event driven simulation system is about 10000 times faster than transistor level simul ation. Experimental results and benchmarks are presented which demonstrates significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation met hods.
This paper presents a efficient approach for the estimation of signal activity figures based on a gate level description of a digital circuit. Exploiting an event oriented simulation system a methodology for calculating very accurate power estimates for digital circuits is presented. A calibration scheme for characterizing the power dissipation of logic gates based on a few key parameters will be outlined. The proposed method proves that the use of an event oriented simulation system calibrated with these gate specific parameters allows power estimations which are comparable to transistor level (SPICE) simulation accuracy. This is essential for the analysis of large circuits, because the proposed event driven simulation system is about 10000 times faster than transistor level simul ation. Experimental results and benchmarks are presented which demonstrates significant improvements in terms of performance, accuracy and flexibility of this approach compared to other state of the art power estimation met hods.
Accurate and fast power estimation of large combinational circuits
A novel probabilistic method to estimate the switching activity of a logic circuit under a real delay gate model, is introduced. Based on Markov stochastic processes and generalizing the basic concepts of zero delay-based methods, a novel probabilistic model to estimate accurately the power consumption, is developed. More specifically, a set of new formulas, which describe first-order temporal correlation, under real delay model, are derived. The chosen gate model allows accurate estimation of the functional and spurious (glitches) transitions, leading to accurate power estimation. The proposed approach manipulates efficiently large circuits employing a new partitioning heuristic, which estimates the switching activity with reduced computational complexity. Comparative study and analysis of benchmark circuits demonstrates the accuracy and efficiency of the proposed method.
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model
VLSI Design, 2001
Our aim is the development of a novel probabilistic method to estimate the power consumption of a combinational circuit under real gate delay model handling temporal, structural and input pattern dependencies. The chosen gate delay model allows handling both the functional and spurious transitions. It is proved that the switching activity evaluation problem assuming real gate delay model is reduced to the zero delay switching activity evaluation problem at specific time instances. A modified Boolean function, which describes the logic behavior of a signal at any time instance, including time parameter is introduced. Moreover, a mathematical model based on Markov stochastic processes, which describes the temporal and spatial correlation in terms of the associated zero delay based parameters is presented. Based on the mathematical model and considering the modified Boolean function, a new algorithm to evaluate the switching activity at specific time instances using Ordering Binary Decision Diagrams (OBBDs) is also presented. Comparative study of benchmark circuits demonstrates the accuracy and efficiency of the proposed method.
Gate-level power estimation using tagged probabilistic simulation
IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 1998
In this paper, we present a probabilistic simulation technique to estimate the power consumption of a CMOS circuit under a general delay model. This technique is based on the notion of a tagged (probability) waveform, which models the set of all possible events at the output of each circuit node. Tagged waveforms are obtained by partitioning the logic waveform space of a circuit node according to the initial and final values of each logic waveform and compacting all logic waveforms in each partition by a single tagged waveform. To improve the efficiency of tagged probabilistic simulation, only tagged waveforms at the circuit inputs are exactly computed. The tagged waveforms of the remaining nodes are computed using a compositional scheme that propagates the tagged waveforms from circuit inputs to circuit outputs. We obtain significant speed up over explicit simulation methods with an average error of only 6%. This also represents a factor of 2-32 improvement in accuracy of power estimates over previous probabilistic simulation approaches.
Power modeling for high-level power estimation
Very Large Scale Integration (VLSI) …, 2000
In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single four-dimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a low-level (typically gate-level) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our table-based model are the average input signal probability, average input transition density, average spatial correlation coefficient and average output zero-delay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one out of about 10,000 cases, the largest error observed was under 20%. If one ignores the glitching activity, then the RMS error becomes under 1%, the average error becomes under 5% and the largest error observed in all cases is under 18%.