CURRENT MODE MULTIPLIER DIVIDER USING TWO OTA (original) (raw)

Related papers

A NOVEL DESIGN OF CURRENT MODE MULTIPLIER/DIVIDER CIRCUITS FOR ANALOG SIGNAL PROCESSING

In analog signal processing, current is used as input variables. In this design current mode multiplier /divider circuits is implemented in two modes. Thus implementing the circuit with proposed concept has very small linearity errors. In addition, high linearity is achieved because high accuracy current mirrors are adopted and the output current is insensitive to the temperature. The proposed computational structures are designed for implementing in 0.18-μm CMOS technology, with a lowvoltage operation (a supply voltage of 1.2 V) excepting with the power consumptions are 55 and 70 μW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.

A Novel Design of Current Mode Multiplier/Divider Circuit Using Translinear Principle

In analog signal processing, current is used as input variables. In this design current mode multiplier /divider circuits is implemented using translinear principle. Thus implementing the circuit with translinear concept has small linearity errors. In addition, high linearity is achieved because high accuracy current mirror is adopted between the squarer circuits and the output current is insensitive to the temperature. The proposed multiplier/divider circuit is designed for implementing in 0.18-μm CMOS technology, with a low-voltage operation (a supply voltage of 1V) excepting with the power consumption of 65μW while their frequency bandwidth is 44MHz.

Current-Mode Multiplier/Divider Circuits Based on the MOS Translinear Principle

Analog Integrated Circuits and Signal Processing, 2001

In this paper, novel current-mode analog multiplier/divider circuits based on a pair of voltage-translinear loops are presented, featuring simplicity, precision and wide dynamic range. They are suitable for standard CMOS fabrication and can be successfully employed in a wide range of analog signal processing applications. Two versions, based on stacked and up-down voltage-translinear loops, respectively, are described. Experimental results are

A novel current-mode four-quadrant CMOS analog multiplier/divider

AEU - International Journal of Electronics and Communications, 2012

This paper presents, a new current mode four-quadrant CMOS analog multiplier/divider based on dual translinear loops. Compared with the previous works this circuit has a simpler structure resulting in lower power consumption and higher frequency response. Simulation results, performed using HSPICE with 0.25um technology, confirm performance of the proposed circuit.

A CMOS current-mode multiplier/divider circuit

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Combination of A/D-D/A converters allows implementing multiplier/divider operations. An efficient design based on continuous-time, current-mode, dividing-algorithmic converters is presented in this paper. It offers high speed and capability of low voltage operation, and it is suitable for applications of low or middle resolution (below 9 bits). In addition, the division result is given in both analog and digital formats. Experimental results from a CMOS prototype with 5 bit resolution are included.

5-V CMOS Current Multiplier/Divider

International Journal of Electrical and Computer Engineering (IJECE), 2018

A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and-3dB small-signal frequency of about 245 MHz. 1. INTRODUCTION Analog multipliers and dividers are very useful sub-circuits in a wide range of signal processing and conditioning applications, such as, analog computation circuits, fuzzy logic controllers and instrumentation systems [1]. They can also be used in communication systems as a programming circuit element, such as, peak detectors and amplitude modulators [2]. Based on the well known current-mode approach, the current multiplier/divider circuit can achieve low supply voltage, low power consumption, large dynamic range, and wide bandwidth. Accordingly, several recent works on analog CMOS current-mode multiplier/divider circuits have been proposed in the literature [3]-[12]. The design approach takes either the exponential I-V relationship of MOS transistors in weak inversion [3]-[6] or their square-law behavior in strong inversion [7]-[12]. In [3]-[5], the translinear loops with MOS transistors operating in the weak inversion mode are used to implementing multiplication and division. The realized circuits are therefore suitable for low-voltage operation and low-power consumption. However, the main limitation of these circuits is that the input dynamic range is very small. The circuits presented in [6]-[10] are not well-suited for low-voltage and low-power applications. A 1.5-V CMOS current multiplier/divider circuit has been reported in [11]. The circuit is based on the use of four compact voltage-to-current converter cells, and also requires additional circuit components to realize the sum and difference of the two input signals i x and i y (i x + i y and i x-i y), which means that the resulting circuit is relatively complex. Additionally, in order to increase an upper-3dB small-signal bandwidth, many analog function circuits can be achieved by utilizing the square-law characteristic of MOS transistors operated in saturation mode [12].

A new high speed and low power four-quadrant CMOS analog multiplier in current mode

AEU - International Journal of Electronics and Communications, 2009

In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 m standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1 MHz, a −3 dB bandwidth of 41.8 MHz and a maximum power consumption of 0.34 mW.

A Versatile General Multiplier Divider Cell by Using Operational Trans-Resistance Amplifiers

Journal of Advance Research in Electrical & Electronics Engineering (ISSN: 2208-2395), 2017

In this paper, we present the design of a versatile general multiplier-divider cell by using the Operational Trans-resistance Amplifier (OTRA) and MOSFETs operating in the linear region. The design and the basic operation of this block is verified. Other operations can also be realized by simply choosing the inputs of the signals at the different terminals. These operations include square root operation, scalar vector multiplier and modulation to name a few. The new cell is reconfigurable and can be programmed by DC voltages. The resulting circuits are simulated by 0.18 m CMOS process through PSPICE. These simulation results verify the versatile operation of this cell.

1.5-V CMOS Current Multiplier/Divider

International Journal of Electrical and Computer Engineering (IJECE)

A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

Analog Integrated Circuits and Signal Processing, 2005

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ±60 µA, the bandwidth is 31 MHz, the input referred noise current is 46 pA/ √ Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ±1V from ±1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 µV/ √ Hz, and the maximum linearity error is 4.1%.