1.5-V CMOS Current Multiplier/Divider (original) (raw)

5-V CMOS Current Multiplier/Divider

International Journal of Electrical and Computer Engineering (IJECE), 2018

A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and-3dB small-signal frequency of about 245 MHz. 1. INTRODUCTION Analog multipliers and dividers are very useful sub-circuits in a wide range of signal processing and conditioning applications, such as, analog computation circuits, fuzzy logic controllers and instrumentation systems [1]. They can also be used in communication systems as a programming circuit element, such as, peak detectors and amplitude modulators [2]. Based on the well known current-mode approach, the current multiplier/divider circuit can achieve low supply voltage, low power consumption, large dynamic range, and wide bandwidth. Accordingly, several recent works on analog CMOS current-mode multiplier/divider circuits have been proposed in the literature [3]-[12]. The design approach takes either the exponential I-V relationship of MOS transistors in weak inversion [3]-[6] or their square-law behavior in strong inversion [7]-[12]. In [3]-[5], the translinear loops with MOS transistors operating in the weak inversion mode are used to implementing multiplication and division. The realized circuits are therefore suitable for low-voltage operation and low-power consumption. However, the main limitation of these circuits is that the input dynamic range is very small. The circuits presented in [6]-[10] are not well-suited for low-voltage and low-power applications. A 1.5-V CMOS current multiplier/divider circuit has been reported in [11]. The circuit is based on the use of four compact voltage-to-current converter cells, and also requires additional circuit components to realize the sum and difference of the two input signals i x and i y (i x + i y and i x-i y), which means that the resulting circuit is relatively complex. Additionally, in order to increase an upper-3dB small-signal bandwidth, many analog function circuits can be achieved by utilizing the square-law characteristic of MOS transistors operated in saturation mode [12].

A NOVEL DESIGN OF CURRENT MODE MULTIPLIER/DIVIDER CIRCUITS FOR ANALOG SIGNAL PROCESSING

In analog signal processing, current is used as input variables. In this design current mode multiplier /divider circuits is implemented in two modes. Thus implementing the circuit with proposed concept has very small linearity errors. In addition, high linearity is achieved because high accuracy current mirrors are adopted and the output current is insensitive to the temperature. The proposed computational structures are designed for implementing in 0.18-μm CMOS technology, with a lowvoltage operation (a supply voltage of 1.2 V) excepting with the power consumptions are 55 and 70 μW, respectively, while their frequency bandwidths are 79.6 and 59.7 MHz, respectively.

Single Low-Supply Current-mode CMOS Analog Multiplier Circuit

2006 International Symposium on Communications and Information Technologies, 2006

A simple structure of low-voltage current-mode CMOS analog multiplier circuit is presented. This multiplier circuit is based-upon quarter square algebraic identity technique by using CMOS technology. The transistors are operated in saturation region for different sub-circuits. The electronic resistor circuits are used as the input stage. The differential amplifiers are used for biased the squaring circuits. The current-mode operation can be obtained with a single supply, low-voltage, high-linearity and wide-bandwidth. This paper consists of 16 NMOSs with a 1.5 volts single supply. The achieved circuit performances have been carried out by PSpice. The input range is obtained more than ±100µA with linearity error less than 1%. The frequency response can be operated larger than 150 MHz.

A CMOS current-mode multiplier/divider circuit

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)

Combination of A/D-D/A converters allows implementing multiplier/divider operations. An efficient design based on continuous-time, current-mode, dividing-algorithmic converters is presented in this paper. It offers high speed and capability of low voltage operation, and it is suitable for applications of low or middle resolution (below 9 bits). In addition, the division result is given in both analog and digital formats. Experimental results from a CMOS prototype with 5 bit resolution are included.

Novel high-precision current-mode multiplier/divider

Analog Integrated Circuits and Signal Processing, 2009

In this paper, a method to reduce the second order effects on the circuit performances caused by the small sized MOS transistors is proposed and a multiplier/divider circuit is designed using this method. The main advantages of the proposed circuit are reduced errors of the output current function, a smaller area on the chip, possibility of controlling the output current with the control voltage, operation at higher frequencies and more efficient power consumption.

CMOS CURRENT MULTIPLIERS IN 0.5µM AND 0.35µM TECHNOLOGY

IAEME PUBLICATION, 2013

A study and comparison between current mode CMOS analog multiplier, ±1.5 V High frequency four quadrant current multiplier and ±1.2 V High frequency four quadrant current multiplier has been carried out in this paper. Current multiplier has been simulated in SPICE with 0.35µm and 0.5µm technology. Simulation has been done with supply voltage of 3.3V, 1.5V and 1.2V respectively. The simulated results show that characteristic of multipliers are linear with 10µA, 30µA and 20µA input range respectively and power dissipation of ±1.2 V High frequency four quadrant current multiplier is less as compared to other circuits in 0.35µm and 0.5µm technology. These circuits are widely used for analog signal processing application.

Improved High Speed Low Power CMOS Multiplier

Third International Conference on Advances in Computing, Electronics and Electrical Technology - CEET 2015, 2015

A high speed four quadrant current mode multiplier is presented. It is based on CMOS devices arranged in dual trans-linear loops and working in saturation region. The designed circuit operates under the voltage supply of ±1.5V. Design simulation was carried out using Tanner EDA Tools v13.0 with level 49 parameters (BSIM3 v3.1) in 0.35µm standard CMOS technology. Simulation results show that the multiplier has a 3dB bandwidth of 440MHz, linearity error of 1.1% and maximum power consumption of 158µW. The analog multiplier is used to carry out amplitude modulation whose results are also reported.

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

Analog Integrated Circuits and Signal Processing, 2005

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ±60 µA, the bandwidth is 31 MHz, the input referred noise current is 46 pA/ √ Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ±1V from ±1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 µV/ √ Hz, and the maximum linearity error is 4.1%.

A new high speed and low power four-quadrant CMOS analog multiplier in current mode

AEU - International Journal of Electronics and Communications, 2009

In this paper a new CMOS current-mode four-quadrant analog multiplier and divider circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 m standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.1%, a THD of 0.97% in 1 MHz, a −3 dB bandwidth of 41.8 MHz and a maximum power consumption of 0.34 mW.

Low Voltage High Performance CMOS Current Mode Four-Quadrant Analog Multiplier Circuit

Radioengineering

This paper describes a new CMOS current-mode four-quadrant analog multiplier circuit. The proposed design is based on a high performance squarer cell, whose main core is realized by the up-down topology trans-linear loop using flipped voltage followers (FVF). The simulation results are verified by TSPICE simulator based on the BSIM3v3 transistor model for TSMC 0.18 µm CMOS process available from level 49 MOSIS at 25°C with ±0.75 V supply voltage. The proposed multiplier offers improved characteristics compared to the multipliers previously exposed in the literature. It has a wide dynamic range. The total harmonic distortion is about 0.42% at 100 kHz with peak-to-peak input current of 40 µA. The −3 dB bandwidth is more than 850 MHz and maximum power consumption is of approximately 105 µW.