Analysis of Electroplating Plant on Different Materials (original) (raw)
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Advanced Cu Electroplating Process for Any Layer Via Fill Applications with Thin Surface Copper
2018
Copper-filled micro-vias are a key technology in high density interconnect (HDI) designs that have enabled increasing miniaturization and densification of printed circuit boards for the next generation of electronic products. Compared with standard plated through holes (PTHs) copper filled vias provide greater design flexibility, improved signal performance, and can potentially help reduce layer count, thus reducing cost. Considering these advantages, there are strong incentives to optimize the via filling process. This paper presents an innovative DC acid copper via fill formulation, for VCP (Vertical Continues Plating) applications which rapidly fills vias while minimizing surface plating. For instance, a 125x75 μm via was filled with only 10 μm Cu deposited on the outer layer surfaces. X-ray diffraction studies were done to obtain information about the grain structure (texture) of the deposit. Based on determination of the Lotgering factor the study shows that the (111) plane has...
2018 13th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2018
The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. There are 4 main drivers which forced the chemical supply industry to introduce new electrolytic copper processes with the new feature of "filling" capability over the years. The 1st driver is the continuous miniaturization of electronics. The first blind microvias were introduced with HDI technology in the late 1980s and early 1990s. In 1996, the IC Substrate market started to fill the micro vias. "Plugging" technologies were introduced in order to stack the micro vias to save space or to create "via in Pad" structures. This "plugging" technology with conductive paste was very expensive because of the additional process steps required. Today copper filled microvias are the standard for almost all HDI PCB manufacturers. The 2nd driver is the thermal management on a substrate. Solutions were needed to integrate features with high thermal conductivity to manage the heat transfer on the substrates from one side to the other in order to minimize hot spots on the electronic devices over a lifetime. The higher the chip performance is, the more it tends to generate local heat-spots resulting in an early loss of the electronics in the field. The reason for this is the degeneration of various materials at these local hot spots. Meanwhile the complete copper filled through holes was realized in 2006, by bridge plating or X-plating technology. Nowadays, completely copper filled through hole structures are at the leading edge of technology for thermal via structures because copper has almost the best thermal conductivity and it has to be plated nonetheless. The 3rd driver is the signal frequency. Electronic signals in an electronic package or inside of a PCB are increasing over time and continue to do so. Stacked microvias and fan-out vias are becoming more and more of a disadvantage for the transmission of high frequency signals, due to the fact of creating resistances at high frequencies. Therefore the push of high frequency applications further increased the demand for technologies like copper filled through holes. The 4th driver especially for through hole filling, is the quality-yield aspect. The alternatives for electroplated copper filled through holes, requires many additional process steps, or new materials such as plugging pastes. Each of these additional process steps or materials introduces a variety of risks and manufacturing problems resulting in lower yield. Therefore the "one step" solution to fill through holes with copper is the preferred solution, without introducing new materials into the PCB. This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs. The paper will contain aspect ratios, dimensions and results of plated through holes used today in high volume manufacturing for microvia and through hole filling with electroplated copper. Furthermore, it will also show feasibility studies of new electroplated structures for future applications such as copper pillar plating on IC-substrates.
2018
Revolutionary new consumer electronic products and their miniaturization drives capitalization on the latest technologies available to increase the functionality of PCBs. High density interconnect (HDI) technology is one of the fastest growing in printed circuit board industry. This technology allow us to utilize the PCB real estate more efficiently by including laser microvias, fine lines and high performance thin materials. The increased density enables more functions per unit area. Advanced HDI technology have multilayer PCBs with copper filled stacked microvias. These Advanced HDI PCBs could house more complex interconnect structures. These very complex structures provide the necessary connection pathways for modern day large pin-count chips. Microvias play crucial role in HDI designs, mechanical or laser drilling of blind micro vias (BMV’s) and successive filling has become the standard manufacturing technique. Specially, small microvias laser drilling is the only possible way ...
High-Aspect-Ratio Copper Via Filling Used for Three-Dimensional Chip Stacking
Journal of The Electrochemical Society, 2003
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced signal delay. Formation of suitable vias by electrodeposition into cavities presents a filling problem similar to that encountered in the damascene process. Because via dimensions for through-chip filling are larger and have a higher aspect ratio relative to features in damascene, process optimization requires modification of existing superconformal plating baths and plating parameters. In this study, copper filling of high-aspect-ratio through-chip vias was investigated and optimized with respect to plating bath composition and applied current wavetrain. Void-free vias 70 m deep and 10 m wide were formed in 60 min using additives in combination with pulse-reverse current and dissolved-oxygen enrichment. The effects of reverse current and dissolved oxygen on the performance of superfilling additives is discussed in terms of their effects on formation, destruction, and distribution of a Cu͑I͒ thiolate accelerant.
2010 Proceedings 60th Electronic Components and Technology Conference (ECTC), 2010
A trench filling type process to fabricate ultra-fine pitch printed wiring boards was developed by combining nanoimprint lithography (NIL) and selective copper deposition. Copper was electorodeposited selectively inside the trenches fabricated in the dielectric layer by NIL process, without causing excess deposition on the surface. The selective deposition was realized by a novel electrodeposition bath employing Cyanine dye as an inhibiting additive. The recessed interconnections with 10 µm line and space dimension were successfully fabricated. The developed process shows significant advantages to the processes employing non-or less-selective deposition, which require planarization to remove excess copper deposited on the surface, and may potentially replace the state of the art semiadditive process.
Improving Copper Electrodeposition in the Microelectronics Industry
IEEE Transactions on Components and Packaging Technologies, 2000
Sporadic voiding within the interfacial Cu 3 Sn intermetallic compound (IMC) layer-sometimes referred to as "Kirkendall voiding"-has been found to lead to degradation of solder joint reliability in board level, mechanical shock testing. It has been suggested that the voiding phenomenon is a result of the incorporation of organic impurities in the copper (Cu) deposit during electroplating. In the present study, Cu samples were electroplated galvanostatically from a generic solution, containing Cl ions, as well as a suppressor [polyethylene glycol (PEG)], and a brightener (bis(3-sulfopropyl) disulfide, SPS) as additives. Overpotential transients were measured during electroplating with a range of current densities (0.5-40 mA cm 2) in baths with various compositions. Effects of the bath chemistry on the Cu surface morphology, as well as on the propensity for voiding after soldering, were also investigated. Elemental analysis of selected samples was performed by SIMS. Plating at 10-20 mA cm 2 with an optimized bath composition led to Cu with a fine-grain structure and smooth appearance. Solder joints formed from these deposits remained void free after soldering and thermal aging. Lower current densities, ran in the same plating bath, led to a significant propensity for voiding, apparently because of incorporation of, principally, SPS and its breakdown products into the growing layer. Continuous plating at 10 mA cm 2 for up to 18 hours without replenishment revealed a strong dependence on bath aging, with Cu changing from "void-proof" to clearly "void-prone." These trends were attributed to the different rates of consumption for PEG and SPS and changes in the contaminants being incorporated in the deposits. In general, differences in the voiding behavior of the plated Cu could be predicted by monitoring a set of characteristic overpotential transient signatures.
High-Aspect-Ratio Copper-Via-Filling for Three-Dimensional Chip Stacking
Journal of The Electrochemical Society, 2005
Through-chip electrodes for three-dimensional packaging can offer short interconnection and reduced signal delay. Formation of suitable vias by electrodeposition into cavities presents a filling problem similar to that encountered in the damascene process. Because via dimensions for through-chip filling are larger and have a higher aspect ratio relative to features in damascene, process optimization requires modification of existing superconformal plating baths and plating parameters. In this study, copper filling of high-aspect-ratio through-chip vias was investigated and optimized with respect to plating bath composition and applied current wavetrain. Void-free vias 70 m deep and 10 m wide were formed in 60 min using additives in combination with pulse-reverse current and dissolved-oxygen enrichment. The effects of reverse current and dissolved oxygen on the performance of superfilling additives is discussed in terms of their effects on formation, destruction, and distribution of a Cu͑I͒ thiolate accelerant.
Fabrication of various micropatterns by maskless micro-electrochemical texturing
Manufacturing Review, 2019
In this paper, an innovative and alternative concept of maskless micro-electrochemical texturing is exploited for the fabrication of simple and complex micropatterns. In this process, the tool is masked incorporated with the textured patterns and the workpiece has no mask. This research study concentrates on generation of simple micropattern, i.e. linear micropattern, and complex micropattern, i.e. cascade micropattern using maskless micro-electrochemical texturing method without repeated use of photolithography process. A single masked patterned tool with SU-8 2150 mask can produce many high-quality simple and complex micropatterns economically using this method. A well-planned experimental setup consisting of electrochemical micromachining (EMM) cell, electrode fixtures, electrical connections and constricted vertical cross-flow electrolyte system has been designed and developed indigenously for carrying out the experiments. Influences of major influencing parameters, i.e. machining voltage, interelectrode gap, flow rate and machining time, are investigated on width overcut and machining depth of micropatterns. For higher machining accuracy, controlled depth and lower standard deviations, machining with lower machining time, lower voltage, lower interelectrode gap and higher flow rate is recommended. From the detailed experimental investigation, the best parametric combination are voltage of 8 V, duty ratio of 30%, pulse frequency of 15 kHz, electrolyte of NaCl (0.34 M) + NaNO 3 (0.23 M), flow rate of 5.35 m 3 /h, interelectrode gap of 50 mm and machining time of 40 s.
Microstructure in electrodeposited copper layers; the role of the substrate
Electrochimica acta, 2001
The microstructures of Cu layers, ranging in thickness from 3 to 12 mm, were investigated. The layers were electrodeposited from an acidic copper electrolyte onto two distinct substrate materials important for the micro-components industry: an Au layer with a pronounced 111-texture, and a nano-crystalline Ni P layer. The evolutions of surface topography, morphology and crystallographic texture in the layers were investigated with scanning electron microscopy (SEM), transmission electron microscopy (TEM) and X-ray diffraction analysis, respectively. Distinct surface topographies were observed for Cu layers deposited on the Au and Ni P substrates. Deposition onto the Au substrate resulted in a very smooth surface of all Cu layers, whereas the Ni P substrate caused an irregular surface for 3-mm-thick layers of Cu. The crystallographic texture in the Cu layers in the first few micrometres depended strongly on the crystallographic texture in the substrate. The Cu crystallites inherited the 111-orientation of the Au substrate, whilst no preferred crystallographic orientation was observed in the Cu crystallites on the nano-crystalline Ni P substrate. For Cu layers thicker than 3 mm a 110-fibre texture developed on both the substrates.