Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits (original) (raw)

Leakage Power Reduction in CMOS Logic Circuit Using Various Techniques

https://www.ijrrjournal.com/IJRR\_Vol.9\_Issue.11\_Nov2022/IJRR-Abstract13.html, 2022

Low power nowadays High-power consumption has turned into a crucial design criterion for VLSI an emerging field. When it comes to energy efficiency, high power dissipation is not thought to be beneficial to battery life in the case of battery-powered applications. It reduces the efficiency, dependability, and cooling expenses of battery life. The high-frequency dynamic variation of inputs is heavily influenced by switching and short-circuit leakage power. There are several common methods for reducing the power consumption of circuits. The average power consumption consists of static and dynamic power consumption. The power consumption comparison of LECT0R, LCNT, Stack 0N0FIC, and SAP0N of various low-power techniques. These circuits are simulated in the cadence tool.

Leakage Power and Area Optimization in Cmos Logic Design in Sub Micron Technology

2017

In VLSI circuits and systems. Due to relatively high complexity of VLSI systems used in various applications, the power dissipation in CMOS inverter arises from its switching activity, which is mainly influenced by the supply voltage and effective capacitance. One of challenge with technology scaling is the rapid increase in sub threshold leakage power due to Vt reduction. Leakage power dissipation is a component of static power dissipation in CMOS circuits. It is caused by the presence of leakage currents in the MOS transistors. Leakage power can be reduce by Stack, Sleep and Sleepy keeper transistor techniques. Sleepy Keeper technique provided lesser static power dissipation and lesser static power delay product in comparison with the other techniques. The main advantage of using Sleepy Keeper technique is that it retains the logic state and also lowers the sub threshold leakage power dissipation. It has been shown previously that the stacking of two off transistors has significan...

Standby Leakage Power Reduction in Digital Circuits

2015

As MOSFET dimensions shrink to the nanometre scale, the leakage power and negative-bias temperature instability (NBTI) become a challenging issue. Leakage power can be decrease by Stack transistor, Sleep transistor and transmission gate base techniques. Sleep transistor technique provided lesser static power dissipation and lesser static power delay product in comparison with the other techniques. It has been shown previously that the stacking of two off transistors has significantly reduced subthreshold leakage compared to a single off transistor. In this work a stack transistor technique using two series connected stack is use to design the digital circuit. But it has a delay penalty. The static and dynamic power of stack is considerably low. But it has a delay penalty and its area requirement is maximum compared with other processes. This can be overcome by using stack transistors of half size. Our goal is to trade off between these limitations and thus propose new methods which ...

A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit

Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style is having two blocks and having a unique characteristic at which we get pre-evaluated output. But the new proposed modified constant logic style and clocked logic style provides better result than the constant logic style. The CMOS technology is used for the simulation process by which the parameter of power is measured which is compared with constant delay logic style.

IJERT-Comparison of Various Leakage Power Reduction Techniques for CMOS Circuit Design

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/comparison-of-various-leakage-power-reduction-techniques-for-cmos-circuit-design https://www.ijert.org/research/comparison-of-various-leakage-power-reduction-techniques-for-cmos-circuit-design-IJERTV2IS100167.pdf Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit types for low-power design centered around inserting controlling transistors between pull-up and pull down circuits as well as between pull-up circuits/pull down circuits and power/ground.We have compared different approach, named “sleepy keeper,” which reduces leakage current while saving exact logic state. Sleepy keeper uses traditional sleep transistors plus two additional transistors – driven by a gate’s already calculated output – to save state during sleep mode. In short, like the sleepy stack approach, sleepy keeper achieves leakage power reduction equivalent to the sleep and other approaches but with the advantage of maintaining exact logic state (instead of destroying the logic state when sleep mode is entered).. Unfortunately, sleepy keeper causes additional dynamic power consumption, approximately 15% more than the base case (no sleep transistors used at all). However, for applications spending the vast majority of time in sleep or standby mode while also requiring low area, high performance and maintenance of exact logic state, the sleepy keeper approach provides a new weapon in a VLSI designer's arsenal