Leakage Power Reduction in CMOS Logic Circuit Using Various Techniques (original) (raw)

Comparative Analysis of Low Power and Low Leakage Reduction for Logic Circuits

IJEER, 2015

As technology scales in nanometer regime leakage current are becoming important metric of comparable importance to leakage current for the analysis and design of complex logic circuits. In this paper, we did the comparative analysis of leakage current for carry look ahead logic circuits. The simulation results depicts that the proposed design leads to efficient in terms of standby leakage power. We have performed simulations using Cadence Spectre 90nm standard CMOS technology at room temperature with supply voltage of 1V.

Leakage Power Reduction in CMOS VLSI Circuits using Advance Leakage Reduction Method

International Journal for Research in Applied Science and Engineering Technology, 2021

Recently, consumption of power is key problem of logic circuits based on Very Large Scale Integration. More potentiality consumption isn’t considered an appropriate for storage cell life for the use in cell operations and changes parameters such as optimality, efficiency etc, more consumption of power also provides for minimization of cell storage cycle. In present scenario static consumption of power is major troubles in logic circuits based on CMOS. Layout of drainage less circuit is typically complex. Several derived methods for minimization of consumption of potentiality for logic circuits based on CMOS. For this research paper, a technique called Advance Leakage reduction (AL reduction) is proposed to reduce the leakage power in CMOS logic circuits. To draw our structure circuit related to CMOS like Inverter, inverted AND, and NOR etc. we have seen the power and delay for circuits. This paper incorporates, analyzing of several minimization techniques as compared with proposed w...

Analysis of Power Dissipation & Low Power VLSI Chip Design

Low power requirement has become a principal motto in today’s world of electronics industries. Power dissipation has becoming an important consideration as performance and area for VLSI Chip design. With reducing the chip size, reduced power consumption and power management on chip are the key challenges due to increased complexity. Low power chip requirement in the VLSI industry is main considerable field due to the reduction of chip dimension day by day and environmental factors. For many designs, optimization of power is important as timing due to the need to reduce package cost and extended battery life. This paper present various techniques to reduce the power requirement in various stages of CMOS designing i.e. Dynamic Power Suppression, Adiabatic Circuits, Logic Design for Low Power, Reducing Glitches, Logic Level Power Optimization, Standby Mode Leakage Suppression, Variable Body Biasing, Sleep Transistors, Dynamic Threshold MOS, Short Circuit Power Suppression.

IJERT-Comparison of Various Leakage Power Reduction Techniques for CMOS Circuit Design

International Journal of Engineering Research and Technology (IJERT), 2013

https://www.ijert.org/comparison-of-various-leakage-power-reduction-techniques-for-cmos-circuit-design https://www.ijert.org/research/comparison-of-various-leakage-power-reduction-techniques-for-cmos-circuit-design-IJERTV2IS100167.pdf Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit types for low-power design centered around inserting controlling transistors between pull-up and pull down circuits as well as between pull-up circuits/pull down circuits and power/ground.We have compared different approach, named “sleepy keeper,” which reduces leakage current while saving exact logic state. Sleepy keeper uses traditional sleep transistors plus two additional transistors – driven by a gate’s already calculated output – to save state during sleep mode. In short, like the sleepy stack approach, sleepy keeper achieves leakage power reduction equivalent to the sleep and other approaches but with the advantage of maintaining exact logic state (instead of destroying the logic state when sleep mode is entered).. Unfortunately, sleepy keeper causes additional dynamic power consumption, approximately 15% more than the base case (no sleep transistors used at all). However, for applications spending the vast majority of time in sleep or standby mode while also requiring low area, high performance and maintenance of exact logic state, the sleepy keeper approach provides a new weapon in a VLSI designer's arsenal

A new leakage reduction method for ultra low power VLSI design for portable devices

Power, Control and Embedded Systems (ICPCES), 2012 2nd International Conference, 2012

Portable electronic devices are integral components in our quotidian life. These devices require charging after a certain amount of usage time. Most of the time during discharging cycle, they remain idle or inactive. If these devices are not in active use, why does the battery discharge? The answer is leakage power consumption. At present the power density in CMOS integrated circuits has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. With downward scaling of technology, static power consumption is becoming more dominant. It is challenging for the circuit designers to balance both scaling and low static power demands. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using stacked sleep transistor without being penalized in power delay product requirement and circuit performance.

LEAKAGE POWER REDUCTION TECHNIQUE IN CMOS CIRCUIT: A STATE-OF-THE-ART REVIEW

The demand for low power devices is increasing vastly due to the fast growth of battery operated applications such as smart phones and other handheld devices. It has become important to control the power dissipation throughout the design cycle beginning from the architectural level to final design at hardware level. Leakage current is the main factor which contributes to almost or more than 50% of total power dissipation. In many new high performance designs, the leakage component of power consumption is comparable to the switching component. More than 40% leakage in SRAM memory is due to leakage in transistors. This survey paper use the design of SRAM architecture to reduce the leakage current and hence the leakage power. The various leakage power reduction techniques have been evolved to tackle the problem and it is still in progress. In this paper mainly, there is study of various leakage power reduction techniques with SRAM architecture in fabrication Technology.