Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops (original) (raw)
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In synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Moreover, the process variations create a large variability in the flip-flop delay in scaled technologies impacting the timing yield. Overtime, many gate sizing algorithms have been introduced to improve the timing yield. This paper presents an analysis of timing yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has a power overhead and PDP overhead of 1.7X and 2.8X, respectively, much higher than that of the transmission-gate master-slave flip flop(TG-MSFF) . The TG-MSFF exhibits the lowest relative power and PDP overheads of 30.87% and 9% ,respectively.
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International Journal on Electrical Engineering and Informatics, 2019
In this work, eight existing master slave single-edge-triggered flip-flops have been analyzed in 130nm process node. A new master slave single-edge-triggered flip-flop has also been proposed. The proposed flip-flop is compared with the existing flip-flops on the basis of power consumption, propagation delay and power delay product (PDP). Special emphasis has been given to power consumption. The power performance of all flip-flops as a function of supply voltage, clock frequency and data activity has been observed. TSpice results of power consumption show that the proposed flip-flop design excels rival designs for all supply voltages; all clock frequencies and all data patterns. Thus the proposed flip-flop is most power efficient flip-flop. This flip-flop also shows the third shortest delay and the second lowest PDP among all discussed flip-flops. The proposed flip-flop is best suitable for systems where low power and low area is of primary interest within a certain timing budget.
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International Journal of Engineering and Technology, 2011
Synchronous logic design is the dominant main stream integrated circuit design methodology. Flip-flops are an inherent building block in any synchronous design. Furthermore flip-flops constitute most of the load on the clock distribution and power networks, which are the main power consuming networks of a synchronous integrated circuit. We survey, design and simulate a superset of flip-flops designed for low power and high performance. We highlight the basic design features of these flip-flops and evaluate them based on timing characteristics, power consumption, and other metrics. Moreover, we propose a new flip-flop design. We go in depth into a finer granularity comparison of the lowest peak power surveyed flip-flops reported in the literature; we show the competitiveness of the new design and make our recommendations.
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In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both highperformance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flipflops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.
Survey and evaluation of low-power flip-flops
International Conference on Computer Design, 2006
Abstract—We survey a set of flip-flops designed for low power and high performance. We highlight the basic features of these flip-flops and evaluate them based on timing characteristics, power consumption, and other metrics.