Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits (original) (raw)
Related papers
Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops
2010
The impact of timing yield improvement under process variation on flip-flops soft error rate
2009
A comparative study of variability impact on static flip-flop timing characteristics
christian bernard, Nadine Azémard
2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
IJERT-Design And Comparison Of Flip-Flops Using CMOS Technology
International Journal of Engineering Research and Technology (IJERT), 2012
Variations in Nanometer CMOS Flip-Flops: Part I—Impact of Process Variations on Timing
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015
Comparative analysis of yield optimized pulsed flip-flops
Design of high performance power efficient flip flops using transmission gates
2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)
A Comparative Analysis Of Power Efficient Flip- Flops
2012
Review of Low Power Design Techniques for Flip-Flops
2018
A low-power CMOS flip-flop for high performance processors
TENCON 2014 - 2014 IEEE Region 10 Conference, 2014
Analysis and design of low-energy flip-flops
2001
Low-Power Flip-Flops: Survey, Comparative Evaluation, and a New Design
International Journal of Engineering and Technology, 2011
Statistical Design Framework of Submicron Flip-Flop Circuits Considering Process Variations
IEEE Transactions on Semiconductor Manufacturing, 2011
Power Efficient Design of Semi-Dynamic Master-Slave Single-EdgeTriggered Flip-Flop
Imran Ahmed Khan (Asst. Prof. D/o Electronics & Comm. Engg.)
International Journal on Electrical Engineering and Informatics, 2019
Flip-Flop Energy/Performance Versus Clock Slope and Impact on the Clock Network Design
IEEE Transactions on Circuits and Systems I: Regular Papers, 2000
Design and analysis of flip flop for low power VLSI applications-A Review
2017
Novel Low Power and Low Transistor Count Flip-Flop Design with High Performance
Imran Ahmed Khan (Asst. Prof. D/o Electronics & Comm. Engg.)
2012
IEEE Journal of Solid-State Circuits, 1999
Power and Delay Optimized Edge Triggered Flip-Flop for low power microcontrollers.
Design of a Low Power and Area Efficient Flip Flop With Embedded Logic Module
Comparative analysis of process variation impact on flip-flops soft error rate
2009
Low-power flip-flop using internal clock gating and adaptive body bias
2006
High-performance energy-efficient D-flip-flop circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2000
Physical design aware selection of energy-efficient and low-energy nanometer flip-flops
2010 International Conference on Microelectronics, 2010
Survey and evaluation of low-power flip-flops
International Conference on Computer Design, 2006
DESIGN AND ANALYSIS OF POWER EFFICIENT SENSE AMPLIFIER BASED FLIP FLOP
IJRCAR, 2014
Design of Semi-Static SET Flip-Flop for Low Power and High Performance Applications
Imran Ahmed Khan (Asst. Prof. D/o Electronics & Comm. Engg.)
2014
Timing yield enhancement through soft edge flip-flop based design
2008 IEEE Custom Integrated Circuits Conference, 2008
Comparative Analysis of low area and low power D Flip-Flop for Different Logic Values
Low Power Multi-Bit Flip-Flops Design for VLSI Applications
2015