Measuring the timing jitter of ATE in the frequency domain (original) (raw)
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IEEE International Frequency Control Sympposium and PDA Exhibition Jointly with the 17th European Frequency and Time Forum, 2003. Proceedings of the 2003
-"Jitter" is the noise modulation due to random time shifts on an otherwise ideal, or perfectly on-time, signal transition. In the absence of ultra-high-speed jitter analyzers, spectrum analysis is an alternate noise measurement for timing jitter. Conventionally, jitter has been defined as a the integral of the phase noise. This paper presents a modified way of calculating timing jitter using phasemodulation (PM) noise measurements of high-speed digital clocks, which considers the frequency response of the jitter analyzer, providing a more accurate map. Measurements of phase noise are typically much more sensitive to phase (or time) fluctuations than a jitter analyzer. A summary table is provided for mapping the results of these measurements in the Fourier frequency domain to jitter in the τ domain for various random (specifically, power-law) noise types, spurs, vibration, and power-supply ripple. In general, one cannot unambiguously map back, that is, translate from jitter measurements to phase noise.
IEEE Transactions on Electromagnetic Compatibility, 2003
A simple model has been developed to characterize electromagnetic interference induced timing variations (jitter) in digital circuits. The model is based on measurable switching parameters of logic gates, and requires no knowledge of the internal workings of a device. It correctly predicts not only the dependence of jitter on the amplitude, modulation depth and frequency of the interfering signal, but also its statistical distribution. The model has been used to calculate the immunity level and bit error rate of a synchronous digital circuit subjected to radio frequency interference, and to compare the electromagnetic compatibility performance of fast and slow logic devices in such a circuit.
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Abstract Phase-locked loops (PLL) in radio-frequency (RF) and mixed analog-digital integrated circuits (ICs) experience substrate coupling due to the simultaneous circuit switching and power/ground (P/G) noise which translate to a timing jitter. In this paper. an analysis of the PLL timing jitter due to substrate noise resulting from P/G noise and large-signal switching is presented. A general comprehensive stochastic model of the substrate and P/G noise sources in very large-scale integration (VLSI) circuits is proposed.
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Measurement, 2011
This paper presents a theoretical analysis of possible jitter impact in application of numeric criterion for fast measurement of frequency by coincidence principle. The primary goal is the generation of a signal containing a known amount of each jitter components. This signal was used for testing signals with regular pulse trains. Initially, jitter components are analyzed and modeled individually. Next, sequences for combining different kinds of jitter are modeled, simulated and evaluated. Jitter model simulation in Matlab is utilized to show the independence of frequency measurement results on the total jitter present in the reference and desired pulse trains independently. A good agreement between previously introduced theory of fast measurement of frequency and simulation in jitter presence is verified; these results allows to engineers use the numeric criterion for fast measurement of frequency in spite to interactions among jitter components in various applications for frequency domain sensors.► We examine constrains of the novel theoretical method of frequency measurement. ► We model four kinds of jitter applied to unknown and reference pulse trains. ► Mixing these kinds of jitter in all possible ways we’re checking measurement quality. ► Increasing intensity of jitter will decrease quality of measuring conditions. ► It is shown that jitter not affects true position of measuring point in our method.
Power Integrity Analysis For Jitter Characterization
2016
The years I spent at the National Institute of Technology have been full of unforgettable memories. Thanks to many people who deserve my highest gratitude. First of all, I am deeply grateful to my academic advisor, Prof. K. K. Mahapatra for the constant support at each step of the process. I would also like to express my appreciation to the Department of Electronics and Communication Engineering, specifically the team of VLSI and Embedded Systems for providing such a friendly and encouraging environment with all the required tools to support high quality academic research. I express my genuine appreciation to Prof. A. K. Swain, Prof. D. P. Acharya and Prof. Nurul Islam, who had presented the universe of VLSI and Embedded System and helped me learning different areas of my specialization. I am very grateful to Mr. Pratik Damle of S. T. Microelectronics for his mentorship and significant contribution to my academic research. I express my soulful gratitude to him for their invaluable guidance for my training and completion of thesis. I am truly appreciative to all my colleagues and different companions who had made my stay at NIT Rourkela and S.T. Microelectronics a charming experience. Last, but not the least, I express my deepest appreciation to my parents, Mr. N. T. Thomas and Mrs. Lilly Thomas and sister Lincy Thomas to whom I owe not only my success but every step of my life. I thank them for the consistent backing and support.
Analysis of jitter due to power-supply noise in phase-locked loops
2000
Abstract Phase-locked loops (PLL) in RF and mixed signal VLSI circuits experience supply noise which translates to a timing jitter. In this paper an analysis of the timing jitter due to the noise on the power supply rails is presented. Stochastic models of the power supply noise in VLSI circuits for different values of on-chip decoupling capacitances are presented first. This is followed by calculation of the phase noise of the voltage-controlled oscillator (VCO) in terms of the statistical properties of supply noise.
Built-in jitter test schemes for mixed-signal integrated circuits
1996
In presenting this thesis in partial fulfilment of the requirements for an advanced degree at the University of British Columbia, I agree that the Library shall make it freely available for reference and study. I further agree that permission for extensive copying of this thesis for scholarly purposes may be granted by the head of my department or by his or her representatives. It is understood that copying or publication of this thesis for financial gain shall not be allowed without my written permission. Department of fJLclf'i rxc*-*' ^
Jitter measurement circuit for mixed signal production test
Measurement, 2007
This paper presents a novel low-cost jitter measurement circuit for production test. The hardware implementation is based on the so-called analytic signal method. The circuit consists of two parts: high-speed ADC sampling and DSP computation. The uniqueness of this circuit comes from the fact that the FPGA is used as both the ADC sampling controller and the main computation engine, which can significantly reduce the test cost. To validate the design effectiveness, measurements results have been compared between various instruments and this proposed circuit.