UCO.MIPSIM: PIPELINED COMPUTER SIMULATOR FOR TEACHING PURPOSES (original) (raw)

A Flexible Simulator of Pipelined Processors

A flexible, parameterizable simulator of pipelined processors is presented. The simulator allows to configure several (micro-)architectural features such as the pipeline depth, the stage in which branch execution occurs, whether or not register file forwarding is performed, and the number of branch delay slots. We use the simulator to perform experiments with three synthetic benchmarks: vector addition, vector summation, and sum of absolute differences. These kernels are representative for data parallel loops, reduction operations, and benchmarks containing many hard to predict branches, respectively.

WebMIPS: a new web-based MIPS simulation environment for computer architecture education

Proceedings of the 2004 workshop on …, 2004

We have implemented a MIPS simulation environment called WebMIPS. Our simulator is accessible from the Web and has been successfully used in introductory computer architecture course at Faculty of Information Engineering in Siena, Italy. The advantages of the Web approach are immediate access to the simulator, without installation, and a possible centralized monitoring of students' activity. WebMIPS is capable of uploading and assembling the MIPS code provided by user, simulating a five-stage pipeline step by step or completely, and displaying the values of all registers, input and output data of all pipeline elements.

Simulators for courses in advance computer architecture

Facta universitatis - series: Electronics and Energetics, 2005

The usage of simulator in teaching computer architecture courses has proven to be the most acceptable way, especially when the simulators offer rich graphical and visual representation of the architecture. In this paper we present several simulators used to teach ILP (Instruction Level of Parallelism) courses. The simulators cover wide area of concepts such as internal logic organization, datapath, control, memory behavior, register renaming, branch prediction, and overall out of order execution. Special dedicated simulators cover details in internal organization like Tomasulo approach and scoreboard for organization of reservation stations. This innovative approach in laboratory exercises is used for advanced ILP course.

Design of a Microsoft Version of MIPS Microprocessor Simulator

2008

We describe the implementation of a MIPS Simulator called MIPS-SIM. MIPS-SIM is a GUI, Java-based simulator for the MIPS assembly language. MIPS, the computer architecture is widely used in industry and is the basis of the popular textbook Computer Organization and Design by David Patterson and John Hennessy, used at over 400 universities. The third edition of this text (published by Morgan Kaufmann in 2005) uses standard 32-bit MIPS as the primary teaching ISA. The MIPS-SIM simulator has been implemented for educational purposes with characteristics that are especially useful to undergraduate computer science and engineering students and their instructors who use the above textbook. MIPS-SIM should be useful in courses such as computer organization and architecture, assembly language programming, and compiler writing. MIPS-SIM implements almost the entire MIPS32 assembler-extended instruction set. MIPS-SIM also provides a simple debugger and minimal set of operating system services. We test MIPS-SIM simulator by running several MIPS assembly programs. Results prove the accuracy, correctness, effectiveness and usefulness of MIPS-SIM.

Procedures based on simulation and hardware for a computer architecture course

Computer Applications in Engineering Education, 2002

In this study, a procedure planning for a Computer Architecture Course that tries to create a balance between simulation and laboratory procedures is presented. For this planning, we use hardware implementation for parts of this subject that require careful dedication because of its complexity: interconnection networks and parallel processing. On the other hand, we use simulation packages for the teaching of pipelined and vectorial processors. ß

The basic microprocessor education simulator

The aim of this study is to teach the principle of microprocessor command executions. This program shows user how the program commands are being executed. There is a field in this simulator users can write own program codes. Also the simulator has an Animation Object (AO). This object can roam on the interface of the simulator. After writing the code simulator compiles user program. In the meantime, error detection is performed and if there is an error related alert is displayed. The software is designed to run each command line separately to demonstrate how it is executed. The software supports four addressing mode, immediate, direct, register indirect and register addressing mode. To show the sub events of the code execution AO drifts on the graphic between related microprocessor units.

Computer Simulator: An Educational Tool for Computer Architecture

American Journal of Applied Sciences, 2006

The great advancement in computer architecture and cache memory design and technology had a considerable influence on the way computer architecture was taught in universities. This requires students to be able to visualize the detailed activities that take place within a computer processor and its interaction with memory system. Computer simulators could effectively be used to enhance the understanding and comprehension of cache memory operation. The main objective of this project was to design and implement a computer simulator that was used as an educational tool. This paper presents design specifications, implementation and the functional and structural components of this simulator. This allows students understand the concepts and theory of the computer hardware topics by constructing and verifying knowledge, testing and comparing several different configurations and memory access. Although there was a large number of computer simulators in the market, this simulator differs in the way it contains a specially designed assembler that feeds the simulator with the binary code. In this context it was a tool that provides a high educational value that, on one hand, helps students learn to write an error-free assembly code and on the other hand comprehend the activities that take place during the execution of the program under different settings. At the front-end of the system there are two parts; the editor and the simulator while at the back-end there are the system specially developed assembler and database.

Teaching Scientific Computing: A Model-Centered Approach to Pipeline and Parallel Programming with C

Scientific Programming, 2015

The aim of this study is to present an approach to the introduction into pipeline and parallel computing, using a model of the multiphase queueing system. Pipeline computing, including software pipelines, is among the key concepts in modern computing and electronics engineering. The modern computer science and engineering education requires a comprehensive curriculum, so the introduction to pipeline and parallel computing is the essential topic to be included in the curriculum. At the same time, the topic is among the most motivating tasks due to the comprehensive multidisciplinary and technical requirements. To enhance the educational process, the paper proposes a novel model-centered framework and develops the relevant learning objects. It allows implementing an educational platform of constructivist learning process, thus enabling learners' experimentation with the provided programming models, obtaining learners' competences of the modern scientific research and computational thinking, and capturing the relevant technical knowledge. It also provides an integral platform that allows a simultaneous and comparative introduction to pipelining and parallel computing. The programming language C for developing programming models and message passing interface (MPI) and OpenMP parallelization tools have been chosen for implementation.

Three Simulator Tools For Teaching Computer Architecture

2001

Teaching computer architecture (at any level) is not an easy task. A critical mass of educators has begun using visualizations of different computer architectures based on simulators to enhance learning. Here we present three representative computer simulators for learning which show: (1) a growing consensus for computer simulation as a teaching tool for complex dynamic processes such as computer architecture and (2) one solution to meet the wide spectrum of target populations and didactic goals for teaching computer organization and architecture. The three simulators we describe are: (1) EasyCPU for the Intel 80X86 family of computer architecture, (2) Little Man Computer for a general von Neumann computer architecture and (3) RTLsim a data-path simulator for a MIPs like CPU. We discuss the additional benefits of computer simulators in terms of flexibility, financial support, obsolesence, accessibility, and research. An appendix is provided for more detailed instructions for each si...