A 6-b 1.6-Gsample/s Flash ADC in 0.18-mum CMOS Using Averaging Termination (original) (raw)
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A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination
IEEE Journal of Solid-State Circuits, 2002
The output averaging technique for input amplifiers of a flash ADC has been analyzed mathematically. Expressions have been derived for the reduction of differential nonlinearity, integral nonlinearity, and the necessary number of overrange amplifiers as a function of the output and averaging resistors. This theory is applied to design a 1.6-Gigasample/s 6-b flash ADC in baseline 0.18-m CMOS technology. A distributed track and hold is implemented to achieve a high sample rate. The small input signal is amplified through a cascade of amplifiers and gradually transformed into robust digital signal levels. An averaging termination circuit has been designed to resemble the infinite string of resistors and amplifiers. By applying termination to the averaging network, the amount of overrange amplifiers and, therefore, the power consumption is reduced, while the linearity and speed performance are maintained. The optimum number of parallel pre-amplifiers is derived on the basis of the tradeoff between the amplifier offset and distortion.
Design and implementation of a low-cost circuit for mediumspeed flash analog to digital conversions
International Journal of Electrical and Computer Engineering (IJECE), 2024
Despite the considerable advancements in analog-to-digital conversion (ADC) circuits, many papers neglect several crucial considerations: Firstly, it does not ensure that ADCs work well in the software or hardware. Secondly, it is not certain that ADCs have a wide range of amplitude responses for the input voltages to be convenient in many applications, especially in electronics, communications, computer vision, CubeSat circuits, and subsystems. Finally, many of these ADCs need to look at the suitability of the proposed circuit to the most extensive range of frequencies. In this paper, a design of a low-cost circuit is proposed for medium-speed flash ADCs. The proposed circuit is simulated based on a set of electronic components with specific values to achieve high stability operation for a wide range of frequencies and voltages, whether in software or hardware. This circuit is practically implemented and experimentally tested. The proposed design aims to achieve high efficiency in the sampling process over a range of amplitudes from 10 mV to 10 V. The proposed circuit operates at a bandwidth of frequencies from 0 Hz to greater than 10 kHz in the simulation and hardware implementation.
2012
Analog-to-Digital Converters (ADCs) are useful building blocks in many applications such as a data storage read channel and an optical receiver because they represent the interface between the real world analog signal and the digital signal processors. Many implementations have been reported in the literature in order to obtain high-speed analog-todigital converters (ADCs). In this paper an effort is made to design 4-bit Flash Analog to Digital Converter [ADC] using 180nm cmos technology. For high-speed applications, a flash ADC is often used. Resolution, speed, and power consumption are the three key parameters for an Analog-to-Digital Converter (ADC). The integrated flash ADC is operated at 4-bit precision with analog input voltage of 0 to 1.8V. The ADC has been designed, implemented & analysed in standard gpdk180nm technology library using Cadence tool.
STUDIES ON CMOS DIGITAL-TO-ANALOG CONVERTERS
2001
In this thesis we present an overview and study on digital-to-analog converters (DAC), mainly for communications applications. Especially, we look at some digital subscriber line (DSL) specifications and communication over twisted-pair channels. It is pointed out that the required resolution on the DACs in such systems is in the order of 12 to 14 bits of resolution. At the same time the bandwidth stretches from below MHz to several tens of MHz. These figures are the guiding specification throughout the thesis.
IJERT-Performance Evaluation Of Different Types Of Analog To Digital Converter Architecture
International Journal of Engineering Research and Technology (IJERT), 2012
https://www.ijert.org/performance-evaluation-of-different-types-of-analog-to-digital-converter-architecture https://www.ijert.org/research/performance-evaluation-of-different-types-of-analog-to-digital-converter-architecture-IJERTV1IS10129.pdf Signal processing is very important in many of the system on-a-chip applications. Analog to digital converters (ADCs) is a mixed signal device that converts analog signals which are real world signals to digital signals for processing the information. A paper present review study of the most popular type of Analog to Digital Converters like flash, pipelined, sigma-delta and successive approximations. The paper represents the fundamental operating principles of these architectures with the sources of error. At last comparison between all analog to digital converters also discussed.
A 45nm Flash Analog to Digital Converter for Low Voltage High Speed System on Chips
In this paper, a 6-bit 1 Gs/sec flash analog-to-digital converter (ADC) for low voltage and high speed system-on-chip (SoC) applications is presented. Simulated with the 45nm Predictive Technology Model, the results demonstrate INL < 0.5LSB, DNL < 0.8LSB and a signal to noise and distortion ratio of 31.9dB. The Threshold Inverter Quantization (TIQ) technique is used with W PMOS /W NMOS < 1 for many transistors to keep the power consumption as low as possible. It is also observed that the ADC consumes 45.42µW of peak power and 8.8µW of average power at full speed while it operates on a power supply voltage of 0.7V. To best of the authors' knowledge, this is the first ADC designed at the 45nm technology node.
A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash–SAR Architecture
IEEE Transactions on Circuits and Systems II: Express Briefs, 2012
This brief presents a 10-bit dual-channel pipelined flash-successive approximation register (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC consists of two channels for high operating speed, and each channel adopts a pipelined flash-SAR architecture for low power and a small area. The proposed flash-SAR ADC in the second stage is composed of a 1-bit flash ADC and a 6-bit SAR ADC considering the chip area, operation speed, and circuit complexity. The prototype ADC fabricated in a 45-nm CMOS process occupies 0.16 mm 2. The differential and integral nonlinearities of the ADC are less than 0.36 and 0.67 LSB, respectively. The ADC shows a signal-to-noise-and-distortion ratio of 54.6 dB and a spurious-free dynamic range of 64.0 dB with a 78-MHz input at 230 MS/s with a 1.1-V supply. The maximum operating frequency of the ADC is 260 MS/s at a 1.2-V supply. The power consumptions of the ADC with 230 and 260 MS/s are 13.9 and 17.8 mW, respectively.
Design techniques and implementation of an 8-bit 200MS/s interpolating/averaging CMOS A/D converter
IEEE Journal of Solid-state Circuits, 2003
The design issues and tradeoffs of a high-speed highaccuracy Nyquist-rate analog-to-digital converter (A/D) converter are described. The presented design methodology covers the complete flow from specifications to verified layout and is supported by both commercial and internally developed computer-aided design tools. The major decisions to be made during the converter's design at both the architectural and the circuit level are described and the tradeoffs are elaborated. The approach is demonstrated for a real-life test case, where a Nyquist-rate 8-bit 200-MS/s 4-2 interpolating/averaging A/D converter was developed in a 0.35-m CMOS technology. The signal-to-noise-plus-distortion ratio at 40 MHz is 42.7 dB and the total power consumption is 655 mW.