On the Impact of Defects Close to the Gate Electrode on the Low-Frequency {1}/f Noise (original) (raw)
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IEEE Electron Device Letters, 2008
This letter studies the impact of defects close to the gate electrode side on low-frequency 1/f noise in the drain and gate current. Defects are selectively introduced by deposition of a submonolayer of HfO 2 dielectric, which induce a large Fermi-level pinning on the gate. Contrary to the common belief that defects at the Si/SiO2 interface are the dominant effect on 1/f noise, defects at the interface and fluctuations in the poly-Si charge are also important.
Appl Phys Lett, 2007
The impact of a submonolayer of HfO2 sandwiched between the SiON gate dielectric and the polycrystalline silicon layer on the low frequency noise of a n-channel metal oxide semiconductor field effect transistor is investigated. Fermi-level pinning at polycrystalline silicon-HfO2 interface acts as a dramatic source of the drain noise due to charge carrier number fluctuations, and of the gate noise due to work function fluctuations. These 1/f noise measurements are a strong indicator that the defects at the top HfO2/polycrystalline silicon interface, rather than bulk defects in the high-k layer, are responsible for the noise degradation observed in HfO2 gate dielectrics.
Applied Physics Letters, 2007
The impact of a submonolayer of HfO 2 sandwiched between the SiON gate dielectric and the polycrystalline silicon layer on the low frequency noise of a n-channel metal oxide semiconductor field effect transistor is investigated. Fermi-level pinning at polycrystalline silicon-HfO 2 interface acts as a dramatic source of the drain noise due to charge carrier number fluctuations, and of the gate noise due to work function fluctuations. These 1 / f noise measurements are a strong indicator that the defects at the top HfO 2 /polycrystalline silicon interface, rather than bulk defects in the high-k layer, are responsible for the noise degradation observed in HfO 2 gate dielectrics.
Gate electrode effects on low-frequency (1/ f) noise in p-MOSFETs with high-κ dielectrics
Solid-state Electronics, 2006
The defects related to the gate-dielectric in high-j-MOSFETs are studied using the 1/f noise technique. Three different types of gate electrodes were used for this purpose -poly-Si, metal (TiN/TaN) and fully Ni Silicided (FUSI) electrodes with Hf-based oxides as the gate dielectric layer. All the three types of devices show a specific behavior near the gate electrode-dielectric interface when the trap profiles are assessed using f · S I spectra. The tunneling depths were calculated and it was found that the high-j oxide (bulk) layers are being probed. From the drain current spectra S I vs. drain current I D of the various gate material devices at given depths, it may be inferred that the concentration of oxygen-vacancy-related defects can significantly influence the 1/f noise performance, which can explain the differences observed in noise between the gate electrodes. Comparison of FUSI gated devices, with various percentages of Hf in the dielectric layer, shows comparable noise levels (S VG ), indicating a minor dependence on Hf-content in the gate dielectric layer.
The Role of the Interfaces in the 1/f Noise of MOSFETs with High-k Gate Stacks
ECS Transactions, 2009
This paper focuses on the impact of the gate and substrate interfaces on the 1/f noise of the drain and the gate current of MOSFETs with high-k gate stacks. Three case studies are critically discussed to highlight the key role played by both interfaces in the 1/f noise. First, we show how a sub-monolayer of HfO 2 sandwiched between SiON gate dielectric and poly-Si gate significantly increases the 1/f noise. The second case study indicates that a LaO cap on top of HfSiON significantly decreases the 1/f noise. The third experiment shows that the 1/f noise can be reduced by increasing the thickness of a SiO 2 interfacial layer sandwiched between the substrate interface and the HfO 2 layer.
Modeling the gate current 1/f noise and its application to advanced CMOS devices
9th International Conference on Solid-State and Integrated-Circuit Technology , 2008
In this work we propose an analytical model for the gate current Ilf noise in CMOS devices. The model is based on a simple idea: one electron trapped in the dielectric switches-off the tunneling through the oxide over an effective blocking area. The model allows evaluating the effective trap density inside the gate dielectric as a function of energy from measurements of the gate current Ilf noise versus gate voltage. Experimental data on advanced CMOS devices confirm the validity and the usefulness of the proposed model.
IEEE Transactions on Electron Devices, 2006
In this paper, complementary measurements of the drain and the gate low-frequency noise are used as a powerful probe for sensing the hafnium-related defects in nMOSFETs with high-k gate stacks and polysilicon gate electrode. Drain noise measurements indicate that for low hafnium content (23%) and thin high-k thickness (2 nm), the defect density at the substrate/dielectrics interface is similar to the case of conventional SiO 2 . Gate-noise measurements suggest that the defect density in the bulk of the high-k gate stacks and at the gate/dielectrics interface is strongly degraded by the hafnium content.
IEEE Transactions on Electron Devices, 2004
Low-frequency noise measurements were performed on p-and n-channel MOSFETs with HfO 2 , HfAlO and HfO 2 Al 2 O 3 as the gate dielectric materials. The gate length varied from 0.135 to 0.36 m with 10.02 m gate width. The equivalent oxide thicknesses were: HfO 2 23 A, HfAlO 28.5 A and HfO 2 Al 2 O 3 33 A. In addition to the core structures with only about 10 A of oxide between the high-dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 A was grown between the highdielectric and Si. DC analysis showed low gate leakage currents in the order of 10 12 A(2 5 10 5 A cm 2 ) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO 2 devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1 8 10 17 cm 3 eV 1 to somewhat higher compared to conventional SiO 2 MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/gate stacks, relative comparison among them and to the Si-SiO 2 system. Index Terms-Flicker noise, hafnium aluminum oxide, hafnium oxide, high-dielectrics, low-frequency noise, MOSFET, 1/f noise.
Low frequency noise in nMOSFETs with subnanometer EOT hafnium-based gate dielectrics
Microelectronics Reliability, 2007
This paper focuses on the noise behavior of nMOSFETs with high-k gate dielectrics (SiON/HfO 2 ) with an equivalent oxide thickness of 0.92 nm and using metal (TiN/TaN) as gate material. From the linear dependence of the normalized drain noise on the gate voltage overdrive we conclude that the 1/f noise is dictated by mobility fluctuations. This behavior is mainly ascribed to the reduced mobility due to the low interfacial thickness of 0.4 nm and the Hf-related defects. The gate current is more sensitive to RTS noise with respect to the drain current noise. Cross-correlation measurements between drain and gate noise are used as a tool for discriminating between noise mechanisms which generate different fluctuation levels at the gate and drain terminal.