CMOS CURRENT MULTIPLIERS IN 0.5µM AND 0.35µM TECHNOLOGY (original) (raw)
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Third International Conference on Advances in Computing, Electronics and Electrical Technology - CEET 2015, 2015
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A simple structure of low-voltage current-mode CMOS analog multiplier circuit is presented. This multiplier circuit is based-upon quarter square algebraic identity technique by using CMOS technology. The transistors are operated in saturation region for different sub-circuits. The electronic resistor circuits are used as the input stage. The differential amplifiers are used for biased the squaring circuits. The current-mode operation can be obtained with a single supply, low-voltage, high-linearity and wide-bandwidth. This paper consists of 16 NMOSs with a 1.5 volts single supply. The achieved circuit performances have been carried out by PSpice. The input range is obtained more than ±100µA with linearity error less than 1%. The frequency response can be operated larger than 150 MHz.
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Bulk-driven technique has been verified to be a promising candidate in the area of low-voltage lowpower techniques. In this paper, current conveyer based-multiplier utilizing bulk-driven technique has been proposed. The proposed circuit was implemented based on CMOS technology to put a step forward in the field of low-voltage low-power applications. The circuit has been simulated at ±0.4 V supply voltage and total power dissipation 60.8 µW. The simulation results have been included to prove the theoretical consideration.
Chinese Journal of Electronics, 2020
This manuscript presents a new four-quadrant analog multiplier using a recently reported current mode active building block, namely the Fully differential second generation current conveyor (FDCCII). The proposed circuit employs single FDCCII and two NMOSFETs only, thus has simple architecture. It is fully-integrable as no other external passive component has been used. Non-ideal behaviour of the reported configuration has been analysed considering current and voltage tracking errors of the FDCCII. Workability of the derived multiplier is verified with PSPICE (Cadence 16.6) simulations using model parameter of TSMC 0.35µm CMOS process and found to be in close agreement with theoretical anticipations. The static power consumption of the circuit is 0.107mW. The circuit works well with good linearity (nonlinearity error ≤ 0.96%) for the input voltage range of ±0.5V for a supply voltage of ±1V and the output is insensitive to temperature variation. Simulation results show that the-3dB bandwidth of the proposed multiplier is 20.67MHz and the output referred noise is less than 9nV/ √ Hz at 1kΩ load condition. Monte-Carlo analysis has also been performed for the proposed configuration. The applicability of the reported multiplier as amplitude modulator, squarer, and frequency doubler are also demonstrated.
1.5-V CMOS Current Multiplier/Divider
International Journal of Electrical and Computer Engineering (IJECE)
A circuit technique for designing a compact low-voltage current-mode multiplier/divider circuit in CMOS technology is presented. It is based on the use of a compact current quadratic cell able to operate at low supply voltage. The proposed circuit is designed and simulated for implementing in TSMC 0.25-m CMOS technology with a single supply voltage of 1.5 V. Simulation results using PSPICE, accurately agreement with theoretical ones, have been provided, and also demonstrate a maximum linearity error of 1.5%, a THD less than 2% at 100 MHz, a total power consumption of 508 W, and -3dB small-signal frequency of about 245 MHz.