Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond (original) (raw)
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Measurement and Simulation of Interconnect Inductance in 90 nm and Beyond
2005 International Conference On Simulation of Semiconductor Processes and Devices, 2005
The on-chip inductance impact on signal integrity has been a problem for designs in deep-submicron technologies. The impact increases clock skew, max-timing and noise levels of bus signals. In this paper, circuit macro-models are benchmarked against test chip measurement in a 90 nm technology. Circuit simulations show the inductive impact on clock skew (e.g., 11ps in 2GHz clock frequency), signal delay (e.g., 11% max-timing push-out) and noise levels (e.g., 13%VDD). In addition, the inductive impact on signal integrity in the presence of process variations is evaluated. Finally, inductive impact in 65nm and 45 nm technologies is simulated, which indicates that the inductance impact will not diminish as technology scales.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005., 2005
On-chip inductance impact on signal integrity, complicated by process variations, becomes challenging for global interconnects in nanometer designs. Simulation and analysis of on-chip buses are presented for the impact of inductance in the presence of process variations. Results show that in 90nm technology there is significant inductive impact on max-timing (~ 9% push-out vs. RC delay) and noise (~ 2x RC noise). Device and interconnect variations add ~ 4% into RLC max-timing impact, while their impact on RLC signal noise is non-appreciable.
Figures of merit to characterize the importance of on-chip inductance
1998
A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful figure of merit. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC Π circuit based on a 0.25 µm IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this study is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect. DAC 98, San Francisco, California © 1998 ACM 1-58113-049-x/98/06 $3.50
Sensitivity of interconnect delay to on-chip inductance
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000
Inductance extraction has become an important issue in the design of high speed CMOS circuits. Two characteristics of on-chip inductance are discussed in this paper that can significantly simplify the extraction of on-chip inductance. The first characteristic is that the sensitivity of a signal waveform to errors in the inductance values is low, particularly the propagation delay and the rise time. It is quantitatively shown in this paper that the error in the propagation delay and rise time is below 9.4% and 5.9%, respectively, assuming a 30% relative error in the extracted inductance. If an RC model is used for the same example, the corresponding errors are 51% and 71%, respectively. The second characteristic is that the magnitude of the on-chip inductance is a slowly varying function of the width of a wire and the geometry of the surrounding wires. These two characteristics can be exploited by using simplified techniques that permit approximate and sufficiently accurate values of the on-chip inductance to be determined with high computational efficiency.
On-Chip Inductance in High Speed Integrated Circuits
2001
A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful figure of merit. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC Π circuit based on a 0.25 µm IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this study is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect. DAC 98, San Francisco, California © 1998 ACM 1-58113-049-x/98/06 $3.50
On the impact of on-chip inductance on signal nets under the influence of power grid noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005
It has been well recognized that the impact of on-chip inductance on some critical nets, such as clock nets, is significant and can not be ignored in delay modeling for these nets. However, the impact of on-chip inductance on signal nets in general is still not well understood. We present results of analyzing inductive effects on signal nets for ultra-deep submicron technologies. The analysis is based on a Al-based 0.18 ¢ ¡ CMOS process and a Cu-based 0.13 ¢ ¡ CMOS process. The impact of on-chip inductance is shown to be insignificant if we assume a perfect power supply network around the interconnect routes. Otherwise, the impact of onchip inductance can be significant. Furthermore, the results presented in this paper illustrate the impact of on-chip inductance one would expect from transitioning from an Albased interconnect technology to a Cu-based interconnect technology.
Accurate capture of timing parameters in inductively-coupled on-chip interconnects
Proceedings of the 17th symposium on Integrated circuits and system design - SBCCI '04, 2004
With continuously increasing on-chip frequencies and shortening signal rise time, inductance effects pose sever difficulties on efficient timing analysis. This work analyses the effects on different timing parameters of the inductive coupling in long and intermediate high-frequency on-chip interconnects. We show that crosstalk, noise, signal integrity, signal rise and fall times, all depend on the data toggling pattern. Moreover, the conclusion is drawn that the worst and best case switching patterns are not necessarily similar for capacitively coupled dominant and for mainly inductively coupled lines.
On-chip interconnect inductance - friend or foe
Fourth International Symposium on Quality Electronic Design, 2003. Proceedings.
Inductance associated with on-chip wires can no longer be ignored as chip operation frequencies increase into GHz regime. Because the magnetic field propagates a very long range, the extraction of wire inductance is not just dependent on the immediate neighboring environment. This paper discusses the various difficulties of extracting inductance of randomly placed wires in a typical chip environment. With dedicated return path, the wire inductance can be controlled and benefit the design of high-speed circuits. Specific examples are illustrated.
Performance criteria for evaluating the importance of on-chip inductance
1998
Two figures of merit are presented for determining whether a section of interconnect should be modeled as either an RL C or an R C impedance. The attenuation that a signal undergoes as it propagates a distance equal to the length of the interconnect line is shown to be a useful figure of merit. The second figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. Circuit simulations of an RLC transmission line and a five section