Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology (original) (raw)
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Microelectronics Journal, 2013
In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting source inductive degeneration technique operating in the frequency range of 3.1-10.6 GHz. In order to achieve low noise figure and high linearity simultaneously, a modified three-stage UWB LNA with inter-stage inductors was proposed. Forward Body-Biased (FBB) technique was used to reduce threshold voltage and power consumption at the first and third stages. The second stage is a push-pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance. The proposed LNA was simulated in standard 0.13 mm CMOS process. A gain of 19.5 7 1.5 dB within the entire band was exhibited. The simulated noise figure (NF) was 1-3.9 dB within the bandwidth. A maximum simulated third-order input intercept point (IIP3) of 4.56 dBm while consuming 4.1 mW from a 0.6 power supply was achieved. The simulated input return loss (S 11) was less than À 5 dB from 4.9 to 12.1 GHz. The output return loss (S 22) was below À 10.6 dB and S 12 was better than À 70.6 dB.
Design and analysis of a 3.1–10.6 GHz Ultra-Wideband Low Noise Amplifier in 0.13μm CMOS
Iranian Scientific Society of Engineering Electromagnetics, 2015
In this paper, a new low complexity ultra-wideband (UWB) 3-10.6 GHz low noise amplifier (LNA) is designed which is consisted of three stages. To overcome the input stage constraints such as broadband impedance matching and high gain while keeping low-power consumption, the combination of the current reuse and reactive feedback technique are applied as the first stage. The second and third stages are common source amplifier with an inductive peaking technique to achieve high flat gain and wide-3 dB bandwidth simultaneously. Analytical formulae are derived for describing the input impedance, gain, and noise figure. The LNA is designed in the standard 0.13 µm CMOS technology which provides 17 dB power gain while consuming 15 mW from a 1-V voltage supply. The average noise figure is 5.5 dB and the simulated input-referred IP3 (IIP3) is-7.7 dBm. The input return loss (S 11) and output return loss (S 22) are less than-10 dB and-25 dB, respectively. The reverse isolation (S 12) is better than-54.52 dB.
Analysis of Low Noise Amplifier Using Cmos in 3GHZ to 10GHZ Range
2016
A 3.1 to 10 GHz Low Noise Amplifier (LNA) with gain enhanced and band-pass property for Ultra Wide Band (UWB) applications using 0.18 µm CMOS technology is designed. Therefore, we proposed a wideband input network with band-pass capability UWB LNA using LC network. It uses a CMOS amplifier with 0.18 µm technology. We have achieved A power gain of 49mW and minimum noise figure of 0.9 dB for the core LNA.
This paper present two new low power, low noise UWB LNA utilizing a inter stage technique with a simple high pass filter and third-order passive Chebychev filter input matching network is proposed. The broad band matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal Noise Figure (NF) and the lower power consumption are also desired. The LNA is designed in the standard 0.18 mum CMOS technology. The implemented two LNA (high pass filter and third-order passive Chebychev filter) present maximum power gain of 16.2 dB and 12 dB, and input return loss then -13.8 dB and -9.5 dB have been achieved and minimum noise figure (NFmin) of 2.05 dB and 2.9 dB was obtained in the frequency range of 3.1-10.6 GHz with a power dissipation of 9.65 mW under a 1.8-V power supply. The proposed UWB LNA demonstrates the highest power gain and lowest NF among the published works in 0.18 mum CMOS technology.
A sub-10mW, noise cancelling, wideband LNA for UWB applications
AEU - International Journal of Electronics and Communications, 2015
Wideband noise cancelling LNAs reported in recent literature consume very large power because of the additional stages required for noise cancelling. This makes them inappropriate for portable applications. Based on this fact, the design of a low power, noise cancelling, wideband LNA is presented in this paper. To demonstrate the proposed circuit, novel use of popular current reuse LNA architecture in combination with the noise cancellation technique is presented. The current reuse architecture aids in obtaining necessary phase difference between signal and noise while providing power optimization. This paper presents detailed mathematical analysis of the modified input impedance, gain and noise figure. The proposed LNA is designed for UWB applications using 130 nm IBM CMOS process. The simulation results demonstrated 3 dB bandwidth of 2.35-9.37 GHz with maximum forward gain (S21) of 10.3 dB and achieved minimum noise figure (NF min ) of 3.68 dB. The simulated input referred third order intercept point (IIP 3 ) and 1 dB compression point (P1dB) are found to be −4 dBm and −12.55 dBm respectively. With a power supply of 1.3 V, the proposed circuit consumes 9.97 mW only.
A low power ultra-wideband CMOS LNA with inter stage technique
2009
This paper present two new low power, low noise UWB LNA utilizing a Inter stage technique with a simple high pass filter and third-order passive Chebychev filter input matching network is proposed . The broad band matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal Noise Figure (NF) and the lower power consumption are also desired. The LNA is designed in the standard 0.18μm CMOS technology. The implemented two LNA (high pass filter and third-order passive Chebychev filter) present maximum power gain of 16.2dB and 12dB, and input return loss then -13.8dB and -9.5dB have been achieved and minimum noise figure (NFmin) of 2.05dB and 2.9dB was obtained in the frequency range of 3.1-10.6GHz with a power dissipation of 9.65mW under a 1.8-V power supply. The proposed UWB LNA demonstrates the highest power gain and lowest NF among the published works in 0.18µ m CMOS technology.
A UWB CMOS low-noise amplifier with noise reduction and linearity improvement techniques
Microelectronics Journal, 2015
In this paper, a highly linear CMOS low noise amplifier (LNA) for ultra-wideband applications is presented. The proposed LNA improves both input second-and third-order intercept points (IIP2 and IIP3) by canceling the common-mode part of all intermodulation components from the output current. The proposed LNA structure creates equal common-mode currents with the opposite sign by cascading two differential pairs with a cross-connected output. These currents eliminate each other at the output and improve the linearity. Also, the proposed LNA improves the noise performance by canceling the thermal noise of the input and auxiliary transistors at the output. Detailed analysis is provided to show the effectiveness of the proposed LNA structure. Post-layout circuit level simulation results using a 90 nm RF CMOS process with Spectre-RF reveal 9.5 dB power gain,-3 dB bandwidth (BW À 3dB) of 8 GHz from 2.4 GHz to 10.4 GHz, and mean IIP3 and IIP2 of þ13.1 dBm and þ42.8 dBm, respectively. The simulated S 11 is less than À 11 dB in whole frequency range while the LNA consumes 14.8 mW from a single 1.2 V power supply.
Fully integrated, highly linear, wideband LNA in 0.13μm CMOS technology
2013 IEEE Symposium on Wireless Technology & Applications (ISWTA), 2013
This paper presents the design of a fully integrated, highly linear, wideband low noise amplifier (LNA). The LNA employs a three stage distributed topology along with input and output matching networks. The transistors have been biased in weak/moderate inversion to achieve better linearity. The post-layout simulation results for the proposed design presents a bandwidth of 0.1-1.9 GHz with an IIP3 of +3.8 dBm and input referred 1-dB CP of-7.72 dBm. The LNA achieves a power gain of 10 dB, NFmin of 4.4 dB and power consumption of 65 mW. With a supply voltage of 2 V, the design has been simulated in Cadence SpectreRF, using IBM 130 nm CMOS technology. The target is to achieve a wide band low noise amplifier that would suffice for multiple standards while offering high linearity.
Analysis of CMOS 0.18 μm UWB low noise amplifier for wireless application
Microsystem Technologies, 2018
In this work, a 0.18 lm CMOS LNA is designed which is favorable for a wireless application and the topology used in this design is cascode inductive source degeneration. This proposed LNA is basically designed for ultra-wideband which will be suitable for RF receiver. For an LNA to be in RF receiver, the LNA must be able to amplify very weak signal of-100 dBm (3.2 uV), must consume very minimum power and lastly, noise generated by LNA must be very small. These requirements are achieved with help of cascode inductive source degeneration topology. This work also presents noise analysis of MOSFET along with LNA's noise and other parameters analysis. Possible types of topologies are also discussed. The proposed LNA provides a good gain of 19.79 dB, an NF of 2.03 dB, reverse isolation (S 12) of-35.2 dB, input return loss (S 11) of-12.2 dB, and output return loss (S 22) of-12 dB, while consuming 10.8 mW from the supply of 1.8 V. The proposed LNA is simulated in Cadence Spectra using 180 nm UMC technology.
A linear current-reused LNA for 3.1-10.6GHz UWB receivers
IEICE Electronics Express, 2008
An ultra-wide-band CMOS low-noise amplifier (LNA) employing a common-gate (CG) stage for wideband input matching is presented. This LNA utilizes the concurrent noise and distortion canceling techniques. Moreover, the current-reused technique exploiting the passive network instead of using the active and power consuming element is introduced to preserve the power consumption while contributing to the noise canceling trend. In other words, this topology is capable of canceling the noise effect of input transistor without consuming much current. Simulation results based on a 0.13 μm standard RFCMOS technology shows that a power gain of 13.5 dB and the noise figure of 2.7-4.2 dB over the −3-dB bandwidth of 2.6-10.7 GHz. With the presence of a weak inversion biased transistor, an input third-order intercept point (IIP3) of +5 dBm is achieved. The power consumption is 13.5 mW from a single 1.2 V power supply.