A sub-10mW, noise cancelling, wideband LNA for UWB applications (original) (raw)
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A highly linear LNA with noise cancellation for 5.8–10.6 GHz UWB receivers
2011
An ultra-wideband (UWB) low-noise amplifier (LNA) with simultaneous noise and distortion cancellation is presented. This LNA utilizes a pMOS in weak inversion for second-and third-order distortion cancellation. By using two inductors, the effective bandwidth for noise/distortion cancellation and input matching are extended. This LNA has been designed in a 0.18-μm CMOS process. The noise figure is 3. GHz. The voltage gain is 13.8 dB while drawing 8.3 mA from 1.8 V supply voltage.
Microelectronics Journal, 2013
In this paper, a low power ultra-wideband (UWB) CMOS LNA was designed exploiting source inductive degeneration technique operating in the frequency range of 3.1-10.6 GHz. In order to achieve low noise figure and high linearity simultaneously, a modified three-stage UWB LNA with inter-stage inductors was proposed. Forward Body-Biased (FBB) technique was used to reduce threshold voltage and power consumption at the first and third stages. The second stage is a push-pull topology exploiting the complementary characteristics of NMOS and PMOS transistors to enhance the linearity performance. The proposed LNA was simulated in standard 0.13 mm CMOS process. A gain of 19.5 7 1.5 dB within the entire band was exhibited. The simulated noise figure (NF) was 1-3.9 dB within the bandwidth. A maximum simulated third-order input intercept point (IIP3) of 4.56 dBm while consuming 4.1 mW from a 0.6 power supply was achieved. The simulated input return loss (S 11) was less than À 5 dB from 4.9 to 12.1 GHz. The output return loss (S 22) was below À 10.6 dB and S 12 was better than À 70.6 dB.
An inductorless wideband LNA with a new noise canceling technique
TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
An inductorless wideband low-noise amplifier (LNA) employing a new noise canceling technique for multistandard applications is presented. The main amplifier has a cascode common gate structure, which provides good input impedance matching and isolation. The proposed noise canceling technique not only improves the noise figure and power gain but also embeds a g m-boosting technique in itself, which reduces the power consumption of the main amplifier. Using current-steering and current-reuse techniques in the noise canceling branch makes the design realizable and low power. The proposed LNA is simulated and optimized in 0.13 µ m CMOS technology. The LNA achieves a noise figure of 2.8-3.4 dB, power gain of 19.2 dB, and input impedance matching better than-10.5 dB over bandwidth of 0.04-4.6 GHz. It consumes only 8.5 mW from 1.2 V supply voltage, which makes it a low power LNA.
A linear current-reused LNA for 3.1-10.6GHz UWB receivers
IEICE Electronics Express, 2008
An ultra-wide-band CMOS low-noise amplifier (LNA) employing a common-gate (CG) stage for wideband input matching is presented. This LNA utilizes the concurrent noise and distortion canceling techniques. Moreover, the current-reused technique exploiting the passive network instead of using the active and power consuming element is introduced to preserve the power consumption while contributing to the noise canceling trend. In other words, this topology is capable of canceling the noise effect of input transistor without consuming much current. Simulation results based on a 0.13 μm standard RFCMOS technology shows that a power gain of 13.5 dB and the noise figure of 2.7-4.2 dB over the −3-dB bandwidth of 2.6-10.7 GHz. With the presence of a weak inversion biased transistor, an input third-order intercept point (IIP3) of +5 dBm is achieved. The power consumption is 13.5 mW from a single 1.2 V power supply.
A 0.7-2.7 GHz Low Power LNA with Noise Cancellation and Current-Reused Technique
Research Square (Research Square), 2022
In this work, a low-power wideband low noise amplifier (LNA) is presented. The proposed LNA is designed based on CG-CS topology which is used for broadband applications. In addition, by adjusting the g m values of the CS stage transistors properly, an attempt has been made to cancel the noise of the CG stage. Moreover, by using the current-reused technique and placing an inductor in the middle node of cascode transistors in the CS stage, it is possible to reduce the impedance caused by the parasitic capacitors of the transistors, which enhance the power gain (S 21). In addition, a g m-boosting technique is adopted to achieve better input impedance matching and reducing the current which pass through the CG stage. And finally, for better linearity results, sweet spot technique has been used to determine the bias voltage of transistors. The LNA has the maximum power gain (S 21) of 18.6dB with a bandwidth of 0.7-2.7GHz, and noise figure of 2.95-3.4dB. It consumes 3.97mW of power from a 1.8V supply excluding testing buffer.
A low power ultra-wideband CMOS LNA with inter stage technique
2009
This paper present two new low power, low noise UWB LNA utilizing a Inter stage technique with a simple high pass filter and third-order passive Chebychev filter input matching network is proposed . The broad band matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal Noise Figure (NF) and the lower power consumption are also desired. The LNA is designed in the standard 0.18μm CMOS technology. The implemented two LNA (high pass filter and third-order passive Chebychev filter) present maximum power gain of 16.2dB and 12dB, and input return loss then -13.8dB and -9.5dB have been achieved and minimum noise figure (NFmin) of 2.05dB and 2.9dB was obtained in the frequency range of 3.1-10.6GHz with a power dissipation of 9.65mW under a 1.8-V power supply. The proposed UWB LNA demonstrates the highest power gain and lowest NF among the published works in 0.18µ m CMOS technology.
This paper present two new low power, low noise UWB LNA utilizing a inter stage technique with a simple high pass filter and third-order passive Chebychev filter input matching network is proposed. The broad band matching and the flat gain are two important factors for the broadband circuits. Besides those factors, the minimal Noise Figure (NF) and the lower power consumption are also desired. The LNA is designed in the standard 0.18 mum CMOS technology. The implemented two LNA (high pass filter and third-order passive Chebychev filter) present maximum power gain of 16.2 dB and 12 dB, and input return loss then -13.8 dB and -9.5 dB have been achieved and minimum noise figure (NFmin) of 2.05 dB and 2.9 dB was obtained in the frequency range of 3.1-10.6 GHz with a power dissipation of 9.65 mW under a 1.8-V power supply. The proposed UWB LNA demonstrates the highest power gain and lowest NF among the published works in 0.18 mum CMOS technology.
Design and Analysis of a Novel Noise Cancelling Topology for Common Gate UWB LNAs
Communications in Computer and Information Science, 2013
In this paper, we present a noise cancellation technique for common gate ultra wide band (UWB) low noise amplifiers (LNAs) which not only reduces the noise but also increases the gain. On implementing this technique in one of the existing UWB LNAs significant reduction of noise figure (NF) compared to same LNA without noise cancellation technique was observed. Noise cancellation of the most dominating thermal noise source viz. the input matching device with theoretical analysis is presented in this paper. Simulation results with TSMC 0.18 μm CMOSRF technology shows a peak gain of 28 dB and base NF of 3.16 dB for a 6.6 GHz (2.4-9 GHz) band LNA with noise cancellation when compared to peak gain of 21 dB and base NF of 4.09 dB without noise cancellation. Both theoretical analysis and simulation results are in good agreement.
Design of UWB low noise amplifier using noise-canceling and current-reused techniques
Integration, 2018
In this paper, an ultra-wideband (UWB) low-noise amplifier (LNA) with low noise-figure (NF) and high power gain (S 21) using 0.18-um CMOS technology is presented, which operates from 3 GHz up to 12 GHz. In the proposed amplifier, a combination of noise-canceling and current-reused technique is used to reduce noise and power consumption, while the gain and the linearity will be improved. The dominant noise source is canceled by the noise-canceling technique. In addition, good input impedance matching is achieved with using both the inductive source degeneration and resistive feedback techniques. The proposed LNA achieves high and flat S 21 of 19.24-20.24 dB and S 11 less than −10 dB for frequencies 3-12 GHz. Additionally, flat NF of 1.72-1.99 dB is achieved for the frequency range of 3-12 GHz. Furthermore, the IIP3 is −5.5 dBm, power consumptions at 1.8-V supply voltage is 23.23 mW and the core layout size is 857.06 µm×770.72 µm.
Ultra-low power LNA design technique for UWB applications
AEU - International Journal of Electronics and Communications, 2018
In this paper, a design technique to improve low noise amplifier (LNA) performance is proposed. This technique is based on a new operating parameter (OP) of MOSFETs for radio frequency (RF) applications. This technique is used to optimize low noise Amplifier (LNA) parameters for Ultra-Wideband (UWB) applications. The presented methodology predicts the optimum biasing point to maximize LNA performance. Simulation results show that the proposed methodology can increase the figure of merit (FoM) by 70 % compared to traditional methodologies, without having a significant effect on either noise figure (NF) or linearity characteristics. Index Terms-low-noise amplifier (LNA), ultra-wideband (UWB), ultra-low-power (ULP), figure of merit (FoM) I. INTRODUCTION RF performance of MOS transistors has been improved due to continuous technology enhancement. In a device domain, short-channel MOSFETs have high-frequency parameters such as transit frequency (f T) which are much higher than 100 GHz in the advanced deep-submicron technology [1]. Although these