Advanced modeling techniques for system-level power integrity and EMC analysis (original) (raw)
Related papers
EMC-aware design on a microcontroller for automotive applications
2009
In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip power rail noise is one of the most detrimental sources of electromagnetic (EM) conducted emissions, since it propagates to the board through the power and ground I/O pads. In this work we investigate the impact of power rail noise on EMI, and we show that by limiting this noise source it is possible to drastically reduce the conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and board designers to asses the power integrity and predict the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.
Application of system-level EM modeling to high-speed digital IC packages and PCBs
IEEE Transactions on Microwave Theory and Techniques, 1997
A system-level electromagnetic (EM) modeling tool combining a three-dimensional (3-D) full-wave finite-element EMfield analysis tool and a time-domain electric-circuit simulator is developed and applied to various geometries such as multilayer printed circuit boards (PCB's), signal lines embedded in a PCB or package, and split power-distribution network. Since the signal integrity is a primary concern of high-speed digital circuits, the noise distributions on various circuit planes are evaluated from the analysis. These noise distributions, often called noice maps, are utilized to identify the location of the major source of simultaneous switching noise (SSN). This information can eventually be adapted for optimum placement of decoupling capacitors to minimize the noise fluctuations on the various circuit planes on an entire PCB. area of EM design and characterization of microwave/millimeter-wave circuits and components and VLSI and MMIC interconnects using the FEM, and development of numerical techniques for analysis and design of high-speed high-frequency circuits with emphasis on parallel/super computing.
Chip-Level Design Constraints to Comply With Conducted Electromagnetic Emission Specifications
IEEE Transactions on Electromagnetic Compatibility, 2012
This paper deals with the reduction of the conducted electromagnetic emissions of microcontrollers caused by the core block switching. The relationship between the conducted emission at the printed circuit board level and the sources of switching noise at the chip level is evaluated through the analysis of an equivalent circuit that comprises an electric model of the internal building blocks of a microcontroller, the model of its package, and that of the board. The model of the integrated circuit is derived on the basis of functional specifications and technology parameters so that it can be extracted before chip manufacturing. By using this model, and knowing the electromagnetic emission limits to be met, the upper bound of the power supply current spectra of the core logic blocks is evaluated and the effectiveness of common spectrum shaping techniques, like the clock-skewing method or the spread-spectrum clock modulation, is discussed.
Application of chip-level EMC in automotive product design
2006 IEEE International Symposium on Electromagnetic Compatibility, 2006. EMC 2006., 2006
Integrated circuits (ICs) are often the source of the high-frequency noise that drives electromagnetic emissions from electronic products. A case study is presented where emissions from a printed circuit board containing an automotive microcontroller are reduced significantly through analysis of the coupling mechanisms from the chip to the board and attached cables. Noise generated by the IC is explored through measurements in a semi-anechoic chamber and TEM cell, through near-field scans, and through modifications to the printed circuit board. Noise is driven by the IC through both power and I/O connections. Results show that a ferrite in series with I/O power in this application reduced emissions by 10 dB or more at critical frequencies. Possible causes for emissions from the IC and modifications that might reduce these emissions are discussed.
IC models accounting for effects of EM noise
2008 International Symposium on Electromagnetic Compatibility - EMC Europe, 2008
This paper addresses the generation of enhanced models of digital ICs. The proposed models accurately represent the effects of the fluctuations of the device port signals induced by EM disturbances coupling to the system interconnect. The models can be easily estimated from the device port transient responses and can be effectively implemented in any commercial tool as SPICE subcircuits. Model accuracy is assessed by comparing measurements carried out on a test board and simulations. The effects of both continuous wave sinusoidal and pulsed disturbances are discussed.
Development and validation of a microcontroller model for EMC
2008 International Symposium on Electromagnetic Compatibility - EMC Europe, 2008
Models of integrated circuits (ICs) allow printed circuit board (PCB) developers to predict radiated and conducted emissions early in board development and allow IC manufactures insight into how to build their ICs better for electromagnetic compatibility (EMC). A model of the power delivery network, similar to the ICEM or LECCS model, was developed for a microcontroller running a typical program and used to predict the noise voltage between the power and return planes of a PCB. The IC and package model was generated using the Apache tool suite. A model of the PCB was created using an electromagnetic cavity model and lumped-element models of components on the board. Values of predicted and measured impedance looking into the IC and PCB matched within a few dB from a few 10s of MHz up to 1 GHz. Measured and predicted values of noise voltage matched within about 6 dB at clock harmonics up to 600-700 MHz.
Accurate Models for Evaluating the Direct Conducted and Radiated Emissions from Integrated Circuits
Applied Sciences
This paper deals with the electromagnetic compatibility (EMC) issues related to the direct and radiated emissions from a high-speed integrated circuits (ICs). These emissions are evaluated here by means of circuital and electromagnetic models. As for the conducted emission, an equivalent circuit model is derived to describe the IC and the effect of its loads (package, printed circuit board, decaps, etc.), based on the Integrated Circuit Emission Model template (ICEM). As for the radiated emission, an electromagnetic model is proposed, based on the superposition of the fields generated in the far field region by the loop currents flowing into the IC and the package pins. A custom experimental setup is designed for validating the models. Specifically, for the radiated emission measurement, a custom test board is designed and realized, able to highlight the contribution of the direct emission from the IC, usually hidden by the indirect emission coming from the printed circuit board. Measurements of the package currents and of the far-field emitted fields are carried out, providing a satisfactory agreement with the model predictions.
Efficient modelling of IC conducted emission for power integrity analysis
Advances in Radio Science
In this paper two methodologies to reduce the complexity of IC conducted emission models for Power Integrity analysis in ICs are presented. The methodologies differ concerning the applicability in simulation tools, complexity and accuracy of the generated models. The first methodology uses a complex model and reduces its order to generate a model with a fewer number of elements. This methodology therefore involves a model order reduction approach. A second minimum complexity, module based modelling approach is introduced for rough estimations, as the order reduced model is still too complex for some applications. The two methodologies are applied to an IC conducted emission model of two digital modules of a 32 Bit microcontroller. The results of the three models are compared and discussed. Fields of application for the introduced modelling approaches are the estimation of the magnitude and time behaviour of the supply current as well as the determination of the number and position of the IC's supply pins.
Indonesian Journal of Electrical Engineering and Computer Science
The proper function of the integrated circuit (IC) in an inhibiting electromagnetic environment has always been a serious concern throughout the decades of revolution in the world of electronics, from disjunct devices to today’s integrated circuit technology, where billions of transistors are combined on a single chip. The automotive industry and smart vehicles in particular, are confronting design issues such as being prone to electromagnetic interference (EMI). Electronic control devices calculate incorrect outputs because of EMI and sensors give misleading values which can prove fatal in case of automotives. In this paper, the authors have non exhaustively tried to review research work concerned with the investigation of EMI in ICs and prediction of this EMI using various modelling methodologies and measurement setups.
Full Chip Signal and Power Integrity with Silicon Substrate Effect
2004
This paper proposes a new method for analyzing signal and power integrity issues on LSI chips. This method can model a full chip power and ground grids considering the effects of transmission line and silicon substrate. A full chip layout data is divided into sections, then each section is modeled as SPICE transmission lines. N-port parameters of the each section are extracted by newly developed super linear solver. The extracted parameters are converted into compact SPICE frequency table. Using this method, the impedance of power/ground grids and dynamic IR drop for signal traces considering full power/ground grids are analyzed. Authors’ Biography Norio Matsui Norio Matsui holds a Ph. D. from Waseda University, Tokyo and was a researcher in NTT Labs for over 16 years. During this period he developed noise simulators integrated with PCB-CAD for Signal and Power Integrity as well as physical designs for high speed tele-switching systems. Apart from authoring numerous papers, he also ...