Full Chip Signal and Power Integrity with Silicon Substrate Effect (original) (raw)
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A system-level electromagnetic (EM) modeling tool combining a three-dimensional (3-D) full-wave finite-element EMfield analysis tool and a time-domain electric-circuit simulator is developed and applied to various geometries such as multilayer printed circuit boards (PCB's), signal lines embedded in a PCB or package, and split power-distribution network. Since the signal integrity is a primary concern of high-speed digital circuits, the noise distributions on various circuit planes are evaluated from the analysis. These noise distributions, often called noice maps, are utilized to identify the location of the major source of simultaneous switching noise (SSN). This information can eventually be adapted for optimum placement of decoupling capacitors to minimize the noise fluctuations on the various circuit planes on an entire PCB. area of EM design and characterization of microwave/millimeter-wave circuits and components and VLSI and MMIC interconnects using the FEM, and development of numerical techniques for analysis and design of high-speed high-frequency circuits with emphasis on parallel/super computing.
Proceedings of the 5th Electronics Packaging Technology Conference (EPTC 2003)
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Circuits, Systems, and Signal Processing, 2018
A semiempirical, piecewise-defined, and physical model for integrated circuit interconnects is presented. The proposed model accurately represents the corresponding frequency-dependent resistance, and self-and mutual inductances while also accounting for the eddy currents induced in the ground metal layer. For the model implementation, different frequency regions where the resistance, and the self-and mutual inductances exhibit different trends due to the variation in the effective area where the current is flowing are identified, as well as the corresponding transitional frequencies. Experimental results performed to on-chip test structures fabricated on an RF-CMOS technology are used to validate the proposed model up to 40 GHz. Keywords Series resistance • Mutual inductance • On-chip interconnects • Ground plane • Integrated circuits • VLSI B Mónico Linares-Aranda
Advanced modeling techniques for system-level power integrity and EMC analysis
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In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, introducing new challenges to ensure the power integrity (PI) of the electronic systems, and increasing the electromagnetic interference (EMI). The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions and modeling techniques to assess and guarantee PI and electromagnetic compatibility (EMC) across the overall system that comprises the chip, package, and printed circuit board (PCB). Hence, PI and EMC/EMI are rapidly becoming a major concern for high-speed circuit, package, and board designers. In this work we investigate the impact of the chip power rail noise on system PI and EMI, and we show that by reducing the power rail noise thus assuring the system PI, it is possible to significantly reduce the electromagnetic (EM) conducted emissions. Furthermore, we present a transistor-level lumped-element simulation model of the system power distribution network (PDN) that allows chip, package, and PCB designers to predict the power integrity and the conducted emissions at critical chip I/O pads. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.
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2001 IEEE MTT-S International Microwave Sympsoium Digest (Cat. No.01CH37157), 2001
For the reliable design of high-speed digital integrated circuits, signal integrity analysis of the critical interconnection lines need to be performed. Such an analysis should account for electromagnetic effects (propagation, impedance mismatch, cross-talk and substrate losses) as well as for the nonlinear behavior of the active circuitry. This work proposes a comprehensive approach to carry-out the above analysis. In particular, an accurate MOSFET analytical model, suitable for advanced submicrometric microelectronic technologies, has been incorporated in a full-wave simulator based on the Lumped Element Finite Difference Time Domain (LE-FDTD) method. In this abstract, discretization and implementation procedures are discussed, and some preliminary simulations, aimed at validating the approach, are presented.