An Overview of Sigma-Delta Converters: How a 1-bit ADC achieves more than 16-bit resolution (original) (raw)
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A 14-bit 80-kHz sigma-delta A/D converter: modeling, design and performance evaluation
IEEE Journal of Solid-State Circuits, 1989
Ilk paper describes the development of a sigma-delta A/D converter. Included is a brief overview of sigma-delta conversion. The A/D converter achieves an 88.5-dB dynamic range and a maximum signal-to-noise ratio of 81.5 dB. The harmonic distortion is negligible. This level of performance is about 10 dB higher than previously reported results for oversampled A/D converters in this frequency range [l], [2]. The analog modulator employs a doubleintegration switched-capacitor architecture with an oversampling rate of 10.24 MHz. Tranxonductance amplifiers having a 16O-MHz f, were developed for the integrators. The circuit is implemented in a 1.75-pm 5-V CMOS process. The analog circuitry occupies 2 mn? of silicon area and consumes 75 mW of power. Some of the difficult problems associated with evaluating the performance of sigma-delta converters are described. The design of a sigma-delta development and performance evaluation system is presented. This system includes a custom interface board linking the chip to a Sun workstation, and extensive digital signal processing and analysis software.
Extended frequency-band-decomposition sigma–delta A/D converter
Analog Integrated Circuits and Signal Processing, 2009
Parallelism can be used to increase the bandwidths of ADC converters based on sigma-delta modulators. Each modulator converts a part of the input signal band and is followed by a digital filter. Unfortunately, solutions using bandpass sigma-delta modulators are very sensitive to the position of the modulators' central frequencies. This paper shows the feasibility of a frequency-band-decomposition (FBD) ADC using continuous time bandpass sigma-delta modulators, even in the case of large analog mismatches. The major benefit of such a solution, called extended-frequency-band-decomposition (EFBD) is its low sensitivity to analog parameters. For example, a relative error in the central frequencies of 4% can be accepted without significant degradation in the performance (other published FBD ADCs require a precision of the central frequencies better than 0.1%). This paper will focus on the performance which can be reached with this system, and the architecture of the digital part. The quantization of coefficients and operators will be addressed. It will be shown that a 14 bit resolution can be theoretically reached using 10 sixth-order bandpass modulators at a sampling frequency of 800 MHz which results in a bandwidth of 80 MHz centered around 200 MHz (the resolution depends on the effective quality factor of the filters of the analog modulators).
Improved performance of multi-bit delta-sigma analog to digital converters via requantization
1991., IEEE International Sympoisum on Circuits and Systems
System performance of an oversampled analog to digital converter (ADC) with feedback noise shaping is limited by the precision of the digital to analog converter (DAC) in the feedback path as well as by the number of integrators in the loop(s): Standard designs avoid the DAC precision problem by restricting the ADC and DAC to a single bit while stability and matching considerations limit systems to three loops. This limit in turn defines the oversample ratio for a given effective bandwidth and noise performance. We present a simple modification to the oversampled ADC which avoids these limitations via requantization in the feedback path of the original delta sigma loop structure. This modification results in greater dynamic range than is available from standard configurations.
A/D Conversion Using Asynchronous Delta-Sigma Modulation and Time-to-Digital Conversion
IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
An analog-to-digital conversion (ADC) scheme based on asynchronous 16 modulation and time-to-digital conversion is presented. An asynchronous 16 modulator translates the analog input to an asynchronous duty-cycle modulated signal. Next, the edge locations are digitally measured using a time-to-digital converter (TDC). This information is then digitally processed into a conventional digital signal. The performance of this novel ADC scheme is theoretically analyzed and verified with simulations. With the proposed digital demodulation algorithm, 11-bit resolution can be obtained with an overcycling ratio (OCR) of only four, which is suitable for high bandwidth applications such as very high bit-rate digital subscriber line (VDSL). When a higher OCR can be tolerated, a gated ring-oscillator (GRO) TDC with an inherent first-order noise shaping property is suggested in combination with a digital continuous-time moving-average (CTMA) filter. This allows for resolutions in excess of 13 bits, which is suitable for ADSL2+. The proposed technique shifts the complexity toward the digital domain, leading to more compact ADC and reduced power consumption, and is, therefore, particularly suited for ADC in ultralow-voltage nanometer technologies that are used for high-speed data communication applications. Index Terms-Analog-to-digital conversion (ADC), asynchronous delta-sigma modulation (ADSM), continuous-time moving-average (CTMA) filter, demodulation, gated ring-oscillator (GRO), time-to-digital conversion. I. INTRODUCTION A LONG WITH THE downscaling of the minimum feature size of modern CMOS technologies, the supply voltage is scaled down accordingly to reduce power dissipation. Reducing the supply voltage, however, increases the design effort and the power consumption for analog circuits even when the required performance is kept constant [1]. Therefore, increasing effort is spent to shift the analog complexity toward the digital domain in an attempt to reduce power consumption while increasing speed and accuracy. Specifically for analog-to-digital Manuscript
A Sigma-Delta Converter with Adjustable Tradeoff between Resolution and Consumption
2007 14th IEEE International Conference on Electronics, Circuits and Systems, 2007
This paper proposes an analog-to-digital converter with two working modes. In the first mode, the system is a sigma-delta passive converter: the analog modulator uses a passive switched-capacitor low-pass filter and the only active element is the comparator. The consumption is low and the resolution is moderate (9 bits). In the second mode, the expected resolution is 15 bits. For that, the passive sigma-delta modulator is put in a loop with a low-pass amplifier and some digital processing elements. The principle of this two-mode system is validated by functional simulations and by the test of a circuit realized in a 0.35µm CMOS technology.
A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC
IEEE Journal of Solid-State Circuits, 2000
The design of a multibit 16converterispresented.It uses a third-order 4-bit 16topologywithdataweightedaveraging (DWA) to reduce the linearity requirements of the digital-to-analog converters in the feedback loop. The implementation of the DWA algorithm is optimized to minimize the delay introduced in the feedback loop, resulting in clock frequencies up to 100 MHz.
2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008
Frequency-Band-Decomposition (FBD) is a good candidate to increase the bandwidths of ADC converters based on sigma-delta modulators. Each modulator processes a part of the input signal band and is followed by a digital filter. In the case of large mismatches in the analog modulators, a new solution, called Extended Frequency-Band-Decomposition (EFBD) can be used. This solution allows for, for example, a four percent error in the central frequencies without significant degradation in the performance when the digital processing part is appeared to the analog modulators. A calibration of the digital part is thus required to reach these theoretical performance. This paper will focus on a self-calibration algorithm for an EFBD. The algorithm helps minimize the quantization noise of the EFBD.
Delta-sigma converters using frequency-modulated intermediate values
Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 1995
This paper describes a new first and secondorder delta-sigma modulator (DSM) concept where the first integrator is extracted and implemented by a FM oscillator with the modulating signal as the input. The result is a simple DSM with no need for DACs, allowing straightforward multi-bit quantization. Without the FM oscillator, the modulator becomes a F/D converter with delta-sigma noise shaping.
Systematic Design Exploration of Delta-Sigma ADCs
IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 2004
An algorithm for architecture-level exploration of the 16 A/D converter (ADC) design space is presented. Starting from the desired specification, the algorithm finds an optimal solution by exhaustively exploring both single-loop and cascaded architectures, with a single-bit or multibit quantizer, for a range of oversampling ratios. A fast filter-level step evaluates the performance of all loop-filter topologies and passes the accepted solutions to the architecture-level optimization step which maps the filters on feasible architectures and evaluates their performance. The power consumption of each accepted architecture is estimated and the best top-ten solutions in terms of the ratio of peak signal-to-noise+distortion ratio versus power consumption are further optimized for yield. Experimental results for two different design targets are presented. They show that previously published solutions are among the best architectures for a given target but that better solutions can be designed as well.
Delta-sigma algorithmic analog-to-digital conversion
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002
Delta-sigma modulation for analog-to-digital conversion resolves a number of bits logarithmic in the number of modulation cycles, and linear in modulation order. As an alternative to higher-order noise shaping, we present an algorithmic scheme that iteratively resamples the modulation residue, by feeding the integrator output back to the input. This yields a bit resolution linear in the number of cycles, similar to an algorithmic analog-to-digital converter. The scheme simplifies the design of the digital decimator to a single shifting counter, and avoids interstage gain errors in conventional algorithmic analog-to-digital converters. Experimental results from an integrated CMOS array of 128 converters show the utility of the design for large-scale parallel quantization in digital imaging and hybrid analogdigital computing. § © incremental converter [2], where a counter implements a rectangular decimation filter. Higher-order § © § © incremental A/D converter. (b) §