Low Power Reversible Parallel Binary Adder/Subtractor (original) (raw)
Related papers
Design of Efficient Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing etc. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible 8-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number gates, Garbage inputs / outputs and Quantum Cost. It is observed that Reversible 8-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I and II.
IRJET-An Efficient Design of 16-bit Parallel ADDER/SUBTRACTOR Using Reversible Gate
In computation because of low power dissipation reversible logic is an attractive field of research in quantum and optical computation. In this brief we design a 16-bit adder/subtractor using 5*5 Parity Preserving Reversible Gate (P2RG).In this method we use the reversible logic gates in place of traditional logic gates like AND gate and OR gate. The function of P2RG adder is same as the traditional adder but the significant of the P2RG is that it works as adder as well as subtractor. The presented P2RG adder reduces the information bit use and loss by reusing the logic information bits logically and realizes the goal of lowering power consumption. It is also efficient in terms of gate count, constant inputs and garbage value.
IJERT-Design and Analysis of Low Power Reversible Adder/Subtractor Circuits
International Journal of Engineering Research and Technology (IJERT), 2020
https://www.ijert.org/design-and-analysis-of-low-power-reversible-adder-subtractor-circuits https://www.ijert.org/research/design-and-analysis-of-low-power-reversible-adder-subtractor-circuits-IJERTV9IS090366.pdf In recent years, reversible logic has become a promising technology in the areas of low power VLSI design, nanotechnology, quantum computing and optical computing. The performance and reliability of digital systems which are now implemented using conventional logic gates can be enhanced by the usage of reversible logic gates, which pave for low power consumption and lesser quantum delays, thus increasing the speed of computation. Adder/subtractor circuits form the fundamental block in the arithmetic and logic unit of processors and other digital logic programmable devices. The performance of a digital system, its speed and throughput depend critically on the way these circuits are designed. Adder circuits are used in the Graphics Processing Unit(GPU) of computers for graphics applications to reduce complexity. Any way to enhance the performance and computational speed of these circuits will pave way for a better ALU. Incorporating the concepts of reversible computing in the design of adder/subtractor circuits can significantly enhance the performance and speed of operation of digital systems. In this paper, two existing adder/subtractor designs and a novel design are compared, analyzed for different bit lengths (1,8,16,32,64). Detailed analysis of reversible logic design parameters, power consumption parameters, and FPGA utilization parameters is carried out. These designs are analyzed and simulated using the Xilinx Vivado tool and implemented on Zedboard Zynq 7000 Evaluation and Development kit(xc7z020clg484-1). The proposed design outperforms the existing designs.
A LOW POWER ADDER USING REVERSIBLE LOGIC GATES
IJRET, 2012
Reversible logic has emerged as one of the most important approaches for the power optimization with its application in low power VLSI design. They are also the fundamental requirement for the emerging field of the Quantum computing having with applications in the domains like Nano-technology, Digital signal processing, Cryptography, Communications. Implementing the reversible logic has the advantages of reducing gate counts, garbage outputs as well as constant inputs. In contrast to conventional gates, reversible logic gates have the same number of inputs and outputs, each of their output function is equal to 1 for exactly half its input assignments and their fan-out is always equal to 1. It is interesting to compare both reversible and conventional gates. In this paper addition, subtraction, operations are realized using reversible logic gates like DKG and TSG gate and compared with conventional gates
Efficient Design Of 4-Bit Binary Adder Using Reversible Logic Gates
This paper proposes the design of 4-bit adder and implementation of adder Reversible logic gate to improve the design in terms of garbage outputs and delay. In the recent years, reversible logic has emerged as a promising technology having its applications in low power CMOS, quantum computing, nanotechnology and optical computing because of it’s zero power dissipation under ideal conditions. Thus, the project will provide the reversible logic implementation of the conventional 4-bit adder using Toffoli gate, Peres gate and using both Peres gate and Fredkin gate. The proposed reversible logic implementation of the 4- bit adder is optimized to obtain minimum number of logic gates and garbage outputs. This project work on the reversible 4-bit adder circuits designed and proposed here form the basis of the decimal ALU of a primitive quantum CPU. The designed and optimized 4-bit reversible adder is implemented in VHDL Using Xilinx ISE 12.1 tool.
International Journal of Modern Education and Computer Science, 2015
This paper proposes a new 4×4 reversible logic gate which is named as MOG. Reversible gates are logical basic units, having equal number of input and output lines, which can reduce power dissipation in digital systems design through their reversibility feature; because there is a one-to-one corresponding between their input and outputs vectors. The most significant aspect of the MOG gate is that it is a universal gate and has the ability of calculating any logical function on its own. We have also proposed quantum representation of the MOG gate with optimal quantum cost equal to 11. Then, it has been proved that MOG gate can be used to produce a cost efficient reversible full adder/subtractor cell in terms of reversible and quantum metrics. The proposed reversible full adder/subtractor design using MOG gate is a completely optimized circuit in terms of the number of reversible gates, the number of constant inputs, and the number of garbage outputs because it can work with the minimum possible amounts of these reversible metrics. Additionally, it is more efficient than the existing counterparts in terms of quantum cost. The full adder/subtractor cell is an important circuit in VLSI and digital signal processing applications. A lot of works have been done toward designing reversible full adder/subtractors in the literature; but there is no an optimized design with quantum implementation. To prove the applicability of the proposed design in large processing scales, we have constructed 8-bits reversible ripple carry full adder/subtractor circuit using MOG gates. Results have shown the superiority of our proposed design compared with other 8-bits similar designs.
ENRICHMENT TOWARDS THE DESIGN OF EFFICIENT 4 BIT REVERSIBLE SUBTRACTOR 2
Reversible logic has widespread employments in quantum computing and low power VLSI design. In the intended work, I will put forward the design, synthesis and simulation of novel reversible subtractor to submit an application of reversible logic. The reversible plan, synthesis and simulation of a 4 bit subtractor will be verified using a reversible TR gate. Idyllically, reversible circuits squander nil energy i.e. zero energy. Thus, it would be of enormous significance to apply reversible logic to designing. The projected effort will be coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using Xilinx ISE Design Suite 14.5.
Full Adder/ Subtractor Using Reversible Logic
2019
Reversible logic is now-a-days emerging as an im-portantresearch area over conventional logic. It is having varietyof applications in fields of Digital Signal Processing, QuantumComputing and Low Power CMOS Design. Irreversiblelogic circuits dissipate heat for every bit of information thatis lost. It is not possible to think of quantum computingwithout implementation of reversible logic. The main purposesof designing reversible logic are to decrease quantumcost, depth of the circuits and the number of garbage outputs.This paper provides the Full adder/subtractor thatuses Half adder/ subtractor with minimum constant inputsand minimum garbage outputs. Thus the proposed architectureFull Adder/ Subtractor is having minimum numberof Constant Inputs and Garbage Outputs than the Existingarchitecture.
DESIGNING A NEW REVERSIBLE ADDER/SUBTRACTOR CIRCUIT FOR LOW POWER ALU APPLICATION
transstellar, 2019
Today, low power loss systems are among the great focus of researchers. Fast and efficient processing systems are in greater demands of this period. In recent years, a huge amount of importance has been given to reversible circuits. The reversible design approach is directed towards the need for the efficient electronic system. It is one of the most important issues at the present time and has many applications such as low power CMOS, nanotechnology, quantum computing, digital signal processing etc. Arithmetic and logic circuits are considered as the important design of any digital calculating systems. In this paper, 4-bit reversible ALU using new reversible Full adder/subtractor is proposed. The proposed design is compared with a existing design in terms of quantum cost, constant input, garbage output and gate count.
Full Adder/Subtractor Circuit Using Reversible Logic Gates
2016
Reversible logic has become one of the most promising areas in the past few decades and has found its application in several technologies. Reversible circuits outperform irreversible circuits in terms of power and delay. This paper presents a novel way of designing 1-bit and 4-bit adder / subtractor using the HNG gate and Perez Gate employing a 6 Transistor approach rather than using the conventional 8 transistor reversible logic. Thereby reducing the number of transistors. Power dissipation and delay are calculated for 1-bit and 4-bit adders using both HNG and Perez gate for various technologies such as 0.35um, 0.18um and 0.6um for 5v, 4v, 3.3v and 3v. The results are obtained using Mentor Graphics tool and has shown significant improvement in terms of power dissipation and delay compared to the irreversible circuits. Keywords— Full Adders, Full Subtractors, Reversible Logic, 4-Bit Adder, 1-Bit Adder, 4-Bit Subtractor,1-Bit Subtractor, HNG Gate, Perez Gate, Feymann Gate, Ripple Car...