Circuits and System Design of RF Polar Transmitters Using Envelope-Tracking and SiGe Power Amplifiers for Mobile WiMAX (original) (raw)
Related papers
2011
This paper presents a broadband cascode SiGe power amplifier (PA) in the polar transmitter (TX) system using the envelope-tacking (ET) technique. The cascode PA achieves the power-added efficiency (PAE) of >30% across the frequency range of 0.6~2.4 GHz in continuous wave (CW) mode. The ET-based polar TX system using this cascode PA is evaluated and compared with the conventional stand-alone cascode PA. The experimental data shows that the cascode PA is successfully linearized by the ET scheme, passing the stringent WiMAX spectral mask and the required error vector magnitude (EVM). The entire polar TX system reaches the PAE of 30%/36% at the average output power of 18/17 dBm at 2.3/0.7 GHz for WiMAX 16QAM 3.5 MHz signals. These measurement results suggest that our saturated cascode SiGe PA can be attractive for dual-mode WiMAX applications.
IEEE Transactions on Circuits and Systems I-regular Papers, 2015
We present a highly efficient RF transmitter over broad average power range using a multilevel envelope-tracking power amplifier (ML-ET PA). The ML-ET PA delivers enhanced efficiency at a back-off power region for handset applications. The supply modulator consists of a linear regulator and a switching converter. The DC supply of the linear regulator is adjusted according to the average power of the envelope signal, and the power-supply-independent class-AB output stage is employed to avoid the crossover distortion generated by the different DC supply voltages. The switch current level is not optimally adjusted by itself following the power back-off level, because the DC supply voltages of the linear regulator and switching converter are different. For the optimum operation over the entire power region, the switch current level is adjusted by detecting the input envelope voltage level. For a 20-MHz long term evolution signal with a 7.5 dB peak-to-average power ratio, the proposed supply modulator delivers a peak voltage of 4.5 V to a 6.5 load with a measured efficiency of 75.9%. The proposed ET PA delivers a power-added efficiency (PAE) of 40%, gain of 28.8 dB, evolved universal terrestrial radio access adjacent channel leakage ratio of 35.3 dBc, and error vector magnitude of 3.23% at an average output power of 27 dBm and an operating frequency of 1.71-GHz. At a 10 dB back-off point, the PAE is improved from 14.5% to 18.7% compared to the conventional ET PA.
SiGe class-E power amplifier with envelope tracking for mobile WiMAX/Wibro applications
2009
In this paper, we report both circuits design and system simulations using highly-efficient monolithic SiGe class-E power amplifier (PA) with an open-loop envelope tracking (ET) technique for mobile WiMAX/Wibro applications. The 1-stage and 2-stage class-E PAs were designed and fabricated in a 0.18 mum BiCMOS SiGe technology. The 1-stage class-E PA achieved peak power added efficiency (PAE) of 62% at output power of 21 dBm in single-tone measurement. The design of linear-assisted switching envelope amplifier is also discussed, which involves balancing the tradeoff between efficiency and signal fidelity. Detailed co-design system simulations including RF circuits and digital DSP blocks show that our class-E PA can be linearized by the open-loop ET technique, and the entire ET-based transmit (TX) system meets the stringent 802.16e TX mask with ~33% overall average efficiency at output power of 18.5 dBm.
A Reconfigurable Power Amplifier for Mobile WIMAX Applications
Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, 2010
This paper presents the design of a reconfigurable power amplifier for Mobile WIMAX applications in the user terminal. The amplifier, which operates from 3.4GHz to 3.5GHz, is based on the Doherty technique. This power efficiency enhancement technique is suitable for modern wireless communications systems, as Mobile WIMAX, that present with high peak-to-average power ratio (PAPR) to target high peak data rates while maintaining a trade-off between efficiency and linearity. In addition, reconfigurability in output power levels is added to the design to adapt it to different power scenarios. This work has been carried out in the framework of the CELTIC project MOBILIA, "Mobility Concepts for IMT-Advanced".
RF CMOS Power Amplifiers for Mobile Terminals
JSTS:Journal of Semiconductor Technology and Science, 2009
Recent progress in development of CMOS power amplifiers for mobile terminals is reviewed, focusing first on switching mode power amplifiers, which are used for transmitters with constant envelope modulation and polar transmitters. Then, various transmission line transformers are evaluated. Finally, linear power amplifiers, and linearization techniques, are discussed. Although CMOS devices are less linear than other devices, additional functions can be easily integrated with CMOS power amplifiers in the same IC. Therefore, CMOS power amplifiers are expected to have potential applications after various linearity and efficiency enhancement techniques are used.
An Optimized 2.4GHz RF Power Amplifier Performance for WLAN System
IOP Conference Series: Earth and Environmental Science, 2013
Recently, the design of RF power amplifiers (PAs) for modern wireless systems are faced with a difficult tradeoff for example, cellphone; battery lifetime is largely determined by the power efficiency of the PA and high spectral efficiency which have ability to transmit data at the highest possible rate for a given channel bandwidth. This paper presents the design a multi stage class AB power Amplifier with high power added efficiency (PAE) and acceptable linearity for the WLAN applications. The open-circuited third harmonic control circuit enhances the efficiency of the PA without deteriorating the linearity of class-AB mode of the PA. The voltage and current waveforms are simulated to evaluate the appropriate operation for the modes. The effectiveness of the proposed controller has been verified by comparing proposed method with another methods using simulation study under a variety of conditions. The proposed circuit operation for a WLAN signals delivers a power-added efficiency (PAE) of 37.6% is measured at 31.6-dBm output power while dissipating 34.61 mA from a 1.8V supply. Finally, the proposed PA is show a good and acceptable result for the WLAN system.
Analysis and design of class-O RF power amplifiers for wireless communication systems
Analog Integrated Circuits and Signal Processing, 2016
In this paper, we present analysis, design and show experimental results of a new type of CMOS based power amplifier (PA) known as class-O Aref et al. (ISSCC Digest of Technical Papers, 2015). Modern CMOS based PAs design is constrained by three fundamental trade-offs, i.e. linearity, efficiency and reliability. More precisely, for a standalone PA, unless advanced and expensive solutions are employed, no such PA architecture exists which is able to meet aforementioned design trade-offs. Theoretical insight is needed to understand the origin of performance trade-offs and the possible solutions to counter them. Class-O is a novel out-of-the-box solution to meet these tough challenges. Our prototype amplifier is a highly linear low-band 706 MHz 4G long term evolution (LTE) compatible class-O RF power amplifier in 130 nm CMOS technology for handheld wireless applications. The class-O architecture uses two sub-amplifiers working together as one grand PA. These two sub-amplifiers are commonsource (CS) and common-drain (CD) amplifiers working in parallel feeding a common load with high linearity without the need for digital predistortion (DPD). The prototype chip is measured and characterized with continuous wave (CW), modulated signal and reliability measurements. With CW measurements, 1-dB compression point (P 1 dB) of 30.6 dBm and peak power added efficiency (PAE) of 45.2 % is achieved. For the modulated signal measurements, the amplifier is tested with 16-QAM 20 MHz LTE signal with peak-to-average-power ratio of 6.54 dB. The amplifier meets the stringent LTE specs with an adjacent channel power ratio (ACPR) less than-30 dBc for both EUTRA and UTRA1 with average output power of 27 dBm and PAE above 20 %. Owing to the voltage following between gate source junctions in the common-drain amplifier in addition to cascode structure of common source amplifier, the stress is significantly reduced at the transistor terminals. The reliability is demonstrated by operating the amplifier in nominal and worst voltage-standing-wave-ratio (VSWR) conditions.
Turkish Journal of Electrical Engineering and Computer Sciences, 2019
Wireless communication standards keep evolving so that the requirement for high data rate operation can be fulfilled. This leads to the efforts in designing high linearity and low power consumption radio frequency power amplifier (RFPA) to support high data rate signal transmission and preserving battery life. The percentage of the DC power of the transceiver utilized by the PA depends on the efficiency of the PA, user data rate, propagation conditions, signal modulations, and communication protocols. For example, the PA of a WLAN transceiver consumes 49% of the overall efficiency from the transmitter. Hence, operating the PA with minimum power consumption without trading-off the linearity is vital in order to achieve the goal of fully integrated system-on-chip (SoC) solution for 4G and 5G transceivers. In this paper, the efficiency in CMOS PA is discussed through the review of multifarious efficiency enhancement techniques in CMOS PA design. This is categorized into the review of efficiency in fundamental classes of PA in which Class E achieves the highest efficiency of 67%, followed by complex architectures utilized to enhance the efficiency level of the PA in which the out-phasing architecture achieved the highest efficiency of 60.7%.
2006 Canadian Conference on Electrical and Computer Engineering, 2006
This paper proposes an experimental study of the architectures of the high power amplification stage and their influences on the system's linearity and power efficiency with application to wireless communication infrastructures. Two architectures are investigated: the single branch power amplification stage using class A/B power amplifiers and the promising multi-branch architecture using dynamic load modulation techniques such as the Doherty amplifier. Two LDMOS based high power amplifiers line-ups operating around 2.14 GHz were designed. In order to improve their efficiency vs. linearity trade-off, a predistortion based linearization technique has been applied to the both studied amplification stages. Measurement results under multi-carriers W-CDMA signals confirm the promising potential of the multibranch approach. Indeed, the multi-branch architecture greatly improves the power efficiency of the amplification stage while maintaining good linearity performances.
Energy saving power amplifier design methodologies for mobile wireless communications
Renewable and Sustainable Energy Reviews, 2015
Energy saving power amplifier design methodologies are gaining increasing momentum in the exponential growth of wireless communications due to the demand of high data rates. The demand in high data rates bottlenecks linear transmission specifications for the power amplifier, thus mandates the device to drain more battery energy. In other words, the efficiency of the PA degrades significantly. The improvement in PA's overall efficiency is possible with the innovation of various circuit topology, which has paved the path to reduce the overall battery energy consumption. In this paper, these techniques are reviewed, explicitly. Also reviewed are recent reported works which attempts low voltage headroom implementation in complementing the reduction of battery energy consumption and design cost through the use of Complementary Metal Oxide Semiconductor (CMOS) process.