Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate (original) (raw)
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IEEE Transactions on Computer-aided Design of Integrated Circuits and Systems, 2009
We propose an efficient method to accurately compute the frequency-dependent impedance of VLSI interconnects in the presence of multilayer conductive substrates. The resulting accuracy (errors less than 3%) and CPU time reduction (more than an order of magnitude) emerge from three different ingredients: a 2-D Green's function approach with the correct quasi-static limit, a modified discrete complex images approximation to the Green's function, and a continuous dipole expansion to evaluate the magnetic vector potential at the short distances that are relevant to VLSI interconnects. This approach permits the evaluation of the self-impedance and mutual-impedance of multiconductor current loops, including substrate effects, in terms of easily computable analytical expressions that involve their relative separations and the electromagnetic parameters of the multilayer substrate.
2008
We propose a computationally efficient method to calculate, with high accuracy, the mutual impedance between two wires in the presence of multilayer substrates, as needed for high frequency CAD applications. The resulting accuracy (errors smaller than 2%) and CPU time reduction (factors of seven) emerge from three different ingredients: a two dimensional Green's function approach with the correct quasi-static limit, a modified discrete complex image approximation to the Green's function, and a novel discrete dipole approximation to evaluate the magnetic vector potential. This approach permits the evaluation of the mutual impedance between two loops in terms of easily computable analytical expressions that involve the relative separations and the electromagnetic parameters of the multi-layer substrate. The results are valid for long wires, for any separation, and for frequencies up to 100 GHz.
3D chip stacking is considered known to overcome conventional 2D-IC issues, using through silicon vias to ensure vertical signal transmission. From any point source, embedded or not, we calculate the impedance spread out; our ultimate goal will to study substrate noise via impedance field method. For this, our approach is twofold: a compact Green function or a Transmission Line Model over a multi-layered substrate is derived by solving Poisson's equation analytically. The Discrete Cosine Transform (DCT) and its variations are used for rapid evaluation. Using this technique, the substrate coupling and loss in IC's can be analyzed. We implement our algorithm in MATLAB; it permits to extract impedances between any pair of embedded contacts. Comparisons are performed using finite element methods.
INDUCTWISE: inductance-wise interconnect simulator and extractor
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2003
A robust, efficient, and accurate inductance extraction and simulation tool, INDUCTWISE, is developed and described in this paper. This work advances the state-of-the-art inductance extraction and simulation techniques, and has several major contributions. First, albeit the great benefits of efficiency, the recently proposed inductance matrix sparsification algorithm, the -method , has a flaw in the stability proof for general geometry. We provide a theoretical analysis as well as a provable stable algorithm for it. Second, a robust window-selection algorithm is presented for general geometry. Third, integrated with the nodal analysis formulation, INDUCTWISE achieves exceptional performance without frequency-dependent complex operations and directly gives time-domain responses. Experimental results show that INDUCTWISE extractor and simulator have dramatic speedup compared to FastHenry and SPICE3, respectively. It has been well tested and released on the web for public usage (Available: http://vlsi.ece.wisc.edu/Inductwise.htm).
Design, Automation, and Test in Europe, 1998
As VLSI circuit speeds have increased, the need for accurate three-dimensional interconnect models has become essential to accurate chip and system design. In this paper, we describe an integral equation approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling along conductors. Unlike previous methods, our approach
On the Extraction of On-Chip Inductance
Journal of Circuits, Systems and Computers, 2003
Inductance extraction has become an important issue in the design of high speed CMOS circuits. Two characteristics of on-chip inductance are discussed in this paper that can significantly simplify the extraction of on-chip inductance. The first characteristic is that the sensitivity of a signal waveform to errors in the inductance values is low, particularly the propagation delay and the rise time. It is quantitatively shown in this paper that the error in the propagation delay and rise time is below 9.4% and 5.9%, respectively, assuming a 30% relative error in the extracted inductance values. If an RC model is used for the same example, the corresponding errors are 51% and 71%, respectively. The second characteristic is that the magnitude of the on-chip inductance is a slow varying function of the width of a wire and the geometry of the surrounding wires. These two characteristics can be exploited by using simplified techniques that permit approximate and sufficiently accurate values of the on-chip inductance to be determined with high computational efficiency.
Inductance Modeling for On-Chip Interconnects
Analog Integrated Circuits and Signal Processing
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization.