Thermal-aware task scheduling at the system software level (original) (raw)
Related papers
Thermal-aware scheduling for future chip multiprocessors
EURASIP Journal on Embedded …, 2007
The increased complexity and operating frequency in current single chip microprocessors is resulting in a decrease in the performance improvements. Consequently, major manufacturers offer chip multiprocessor (CMP) architectures in order to keep up with the expected performance gains. This architecture is successfully being introduced in many markets including that of the embedded systems. Nevertheless, the integration of several cores onto the same chip may lead to increased heat dissipation and consequently additional costs for cooling, higher power consumption, decrease of the reliability, and thermal-induced performance loss, among others. In this paper, we analyze the evolution of the thermal issues for the future chip multiprocessor architectures and show that as the number of on-chip cores increases, the thermal-induced problems will worsen. In addition, we present several scenarios that result in excessive thermal stress to the CMP chip or significant performance loss. In order to minimize or even eliminate these problems, we propose thermal-aware scheduler (TAS) algorithms. When assigning processes to cores, TAS takes their temperature and cooling ability into account in order to avoid thermal stress and at the same time improve the performance. Experimental results have shown that a TAS algorithm that considers also the temperatures of neighboring cores is able to significantly reduce the temperature-induced performance loss while at the same time, decrease the chip's temperature across many different operation and configuration scenarios.
Temperature-Aware Microarchitecture: Extended Discussion and Results
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package's capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies.
Temperature-aware microarchitecture : extended results and discussion
2003
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processor-level techniques that can regulate operating temperature when the package's capacity is exceeded. Evaluating such techniques, however, requires a thermal model that is practical for architectural studies.
Thermal-aware application scheduling on device-heterogeneous embedded architectures
— The challenges of the Power Wall manifest in mobile and embedded processors due to their inherent thermal and form-factor constraints. The power dissipated over a fixed area, namely, the power density, directly affects acceptable core temperatures even for low-power devices. In this paper, we examine techniques to counter this power density increase with device and microarchitecture-level heterogeneity. We explore the design space in which various parameters such as frequency and micro-architectural complexity can be traded off against each other in order to achieve the optimal configuration for a fixed temperature limit. Since conventional CMOS technology based cores may not satisfy our performance and power requirements, especially under tight thermal constraints, we propose a heterogeneous CMOS-Tunnel FET multicore for obtaining the optimal operating points under power and thermal limitations. Using a profiling based static assignment scheme, we demonstrate the improvement obtained by coupling this device-level heterogeneity to architectural modifications. We also propose an instruction slack-based scheme to map applications on the heterogeneous multicore. Our schemes show an improvement of up to 47% performance and 30% energy above the best homogeneous configuration.
An online temperature-aware scheduling technique to avoid thermal emergencies in multiprocessor systems, 2019
Reliability, performance and power consumption of a real-time multiprocessor system are negatively affected by high temperatures, spatial gradients and thermal cycles. Software-based load balancing techniques have been used for thermal management. The transfer of workload in such techniques is based on temperature estimation. In this paper, we proposed an online temperature-aware scheduling technique that performs load balancing based on dynamic temperature measurement at a fixed ambient temperature. Contrary to the static techniques that utilize the principle of temperature prediction, the proposed technique does not require any thermal history of workload and is effective for any kind of workload without prior knowledge. Moreover, it reduces the energy consumption and avoids the workload switching delays among the cores. The simulation results show that the technique reduces overall temperature up to 5%, thermal cycles up to 3% and lowers the temporal and spatial gradients compared to the commonly used techniques .
Thermal aware task sequencing on embedded processors
Proceedings of the 47th Design Automation Conference, 2010
We seek to maximize the throughput of a periodic application by obtaining an optimized task sequence and dynamic voltage/freque-cy scaling schedules subject to a peak temperature constraint. We first derive an optimal initial temperature that can generate optimum solutions. We next present optimal solutions for several subproblems. Finally, we propose novel algorithms for the general instances of the problem. Experimental results show that our techniques out perform existing approaches in both design quality and solution times.
Temperature and energy aware scheduling of heterogeneous processors
2016 Ninth International Conference on Contemporary Computing (IC3), 2016
Modern computing requires faster and more powerful processing. Faster and more powerful processors have resulted in higher heat dissipation and power consumption. In this paper we present an offline algorithm called Temperature and Energy aware Dynamic Level Scheduling (TEDLS). It is able to schedule tasks in a heterogeneous environment with DVS enabled processors to minimize execution time, energy consumption and heat dissipation. We use a heat model to estimate the final temperature of a processor executing a task. This estimation of temperature is based on processor characteristics, which aids in choosing the cooler processors. Our simulation results have shown that the TEDLS algorithm not only results in processors having lower temperatures but also produces lower energy consumption as compared to the previous offline algorithms. The TEDLS algorithm also produces lower application execution time when the application size is small.
Temperature-aware scheduling: When is system-throttling good enough
Power-aware operating systems ensure that the system temperature does not exceed a threshold by utilizing system-throttling. In this technique, the system load (or alternatively, the clock speed) is scaled when the temperature hits this threshold. At other times, the system operates at maximum load.
Efficient Implementation of Thermal-Aware Scheduler on a Quad-core Processor
2011
Due to power wall and slow performance improvement in a single core micro-architecture, multiple even many cores based processors rose as the main stream processor. Nevertheless, thermal threats regarding reliability and lifetime of processors are still among the major concerns which received much attention in terms of algorithms and hardware design to reduce processor temperature and keep application performance in recent years. In this paper, we propose and implement a thermal-aware Round-Robin scheduling algorithm for process migration in the Linux environment on a quad-core processor. Bearing designer's goals in mind, such as performance, load-balancing, and reliability, we managed to achieve much bigger temperature fall than previous results of Round-Robin scheduler on a dual-core processor as well as baseline Linux scheduler on a quad-core processor. Moreover, the performance loss due to scheduling overhead is modest in our approach. Our results indicate that thermal-aware scheduling is a valid approach to tackling thermal issues on multi-core processors. There will be increasing demand for thermal-aware scheduling as the number of cores on a single processor increases.
Sustainable Computing: Informatics and Systems, 2011
Temperature-aware techniques have established themselves as crucial steps during the design and operation of new complex ICs (e.g. dual-core microprocessors) in order to protect the ICs against high temperatures that may drastically reduce their lifetime or even render them inoperable. These techniques have been developed after it became clear that power-aware techniques and low-power design are insufficient since they still allowed hotspots to develop in the chip with temperatures considerably higher than the average temperature. The goal of this paper is to provide an overview of the state-of-the-art of temperature-aware computing. After a brief introduction, we present the current approaches to measuring the temperature of a circuit during its operation and to estimating, during the design phase, the maximum temperature that the circuit will experience. We then survey the known techniques for designing a chip with lower maximum temperature. This is followed by reviewing the currently employed run-time temperature management techniques. This paper presents a thorough review of the research done in the past decade or so in the field of thermal-aware computing and lists most of the relevant journal and conference papers on this topic.