Thermal aware task sequencing on embedded processors (original) (raw)

Thermal-aware task scheduling at the system software level

Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07, 2007

Power-related issues have become important considerations in current generation microprocessor design. One of these issues is that of elevated on-chip temperatures. This has an adverse effect on cooling cost and, if not addressed suitably, on chip reliability. In this paper we investigate the general trade-offs between temporal and spatial hot spot mitigation schemes and thermal time constants, workload variations and microprocessor power distributions. By leveraging spatial and temporal heat slacks, our schemes enable lowering of on-chip unit temperatures by changing the workload in a timely manner with Operating System(OS) and existing hardware support.

Algorithms for Temperature-Aware Task Scheduling in Microprocessor Systems

Lecture Notes in Computer Science, 2008

We study scheduling problems motivated by recently developed techniques for microprocessor thermal management at the operating systems level. The general scenario can be described as follows. The microprocessor's temperature is controlled by the hardware thermal management system that continuously monitors the chip temperature and automatically reduces the processor's speed as soon as the thermal threshold is exceeded. Some tasks are more CPU-intensive than other and thus generate more heat during execution. The cooling system operates non-stop, reducing (at an exponential rate) the deviation of the processor's temperature from the ambient temperature. As a result, the processor's temperature, and thus the performance as well, depends on the order of the task execution. Given a variety of possible underlying architectures, models for cooling and for hardware thermal management, as well as types of tasks, this scenario gives rise to a plethora of interesting and never studied scheduling problems.

Architecture-aware Task-scheduling: A thermal approach

2011

Current task-centric many-core schedulers share a "naive" view of processor architecture; a view that does not care about its thermal, architectural or power consuming properties. Future processor will be more heterogeneous than what we see today, and following Moore's law of transistor doubling, we foresee an increase in power consumption and thus temperature. Thermal stress can induce errors in processors, and so a common way to counter this is by slowing the processor down; something task-centric schedulers should strive to avoid. The Thermal-Task-Interleaving scheduling algorithm proposed in this paper takes both the application temperature behavior and architecture into account when making decisions. We show that for a mixed workload, our scheduler outperforms some of the standard, architecture-unaware scheduling solutions existing today.

Feasibility Analysis for Temperature Constrained Real-Time Scheduling on Multi-Core Platforms

Multi-core platforms are becoming the primary choice to achieve high performance in embedded system design. At the same time, the exponential increases in transistor density and power consumption have made the thermal issue a critical concern. In this paper, we study the problem on how to determine if a periodic dynamic frequency scaling (DVFS) schedule for a multi-core platform can satisfy a given maximum temperature constraint. We first develop a novel method to quickly and analytically calculate the temperature at an arbitrary time of a periodic schedule. We then develop three feasibility checking algorithms to test if a periodic DVFS schedule exceeds a given peak temperature limit. Our experiments, based on HotSpot-5.0 simulator under 65nm IC technology, show that the proposed temperature calculation method has no more than 1.5 o C difference in accuracy and 100 times faster in computational time, and also demonstrate the effectiveness of our feasibility checking conditions.

Feasibility Analysis for Temperature-Constraint Hard Real-Time Periodic Tasks

IEEE Transactions on Industrial Informatics, 2000

Thermal-aware scheduling for future chip multiprocessors

EURASIP Journal on Embedded …, 2007

The increased complexity and operating frequency in current single chip microprocessors is resulting in a decrease in the performance improvements. Consequently, major manufacturers offer chip multiprocessor (CMP) architectures in order to keep up with the expected performance gains. This architecture is successfully being introduced in many markets including that of the embedded systems. Nevertheless, the integration of several cores onto the same chip may lead to increased heat dissipation and consequently additional costs for cooling, higher power consumption, decrease of the reliability, and thermal-induced performance loss, among others. In this paper, we analyze the evolution of the thermal issues for the future chip multiprocessor architectures and show that as the number of on-chip cores increases, the thermal-induced problems will worsen. In addition, we present several scenarios that result in excessive thermal stress to the CMP chip or significant performance loss. In order to minimize or even eliminate these problems, we propose thermal-aware scheduler (TAS) algorithms. When assigning processes to cores, TAS takes their temperature and cooling ability into account in order to avoid thermal stress and at the same time improve the performance. Experimental results have shown that a TAS algorithm that considers also the temperatures of neighboring cores is able to significantly reduce the temperature-induced performance loss while at the same time, decrease the chip's temperature across many different operation and configuration scenarios.

Temperature and energy aware scheduling of heterogeneous processors

2016 Ninth International Conference on Contemporary Computing (IC3), 2016

Modern computing requires faster and more powerful processing. Faster and more powerful processors have resulted in higher heat dissipation and power consumption. In this paper we present an offline algorithm called Temperature and Energy aware Dynamic Level Scheduling (TEDLS). It is able to schedule tasks in a heterogeneous environment with DVS enabled processors to minimize execution time, energy consumption and heat dissipation. We use a heat model to estimate the final temperature of a processor executing a task. This estimation of temperature is based on processor characteristics, which aids in choosing the cooler processors. Our simulation results have shown that the TEDLS algorithm not only results in processors having lower temperatures but also produces lower energy consumption as compared to the previous offline algorithms. The TEDLS algorithm also produces lower application execution time when the application size is small.

Approximation algorithm for the temperature-aware scheduling problem

2007 IEEE/ACM International Conference on Computer-Aided Design, 2007

The paper addresses the problem of performance optimization for a set of periodic tasks with discrete voltage/frequency states under thermal constraints. We prove that the problem is NP-hard, and present a pseudo-polynomial optimal algorithm and a fully polynomial time approximation technique (FPTAS) for the problem. The FPTAS technique is able to generate solutions in polynomial time that are guaranteed to be within a designer specified quality bound (QB) (say within 1% of the optimal). We evaluate our techniques by experimentation with multimedia and synthetic benchmarks mapped on the 70nm CMOS technology processor. The experimental results demonstrate our techniques are able to match optimal solutions when QB is set at 5%, can generate solutions that are quite close to optimal (< 5%) even when QB is set at higher values (50%), and executes in few seconds (with QB > 25%) for large task sets with 120 nodes (while the optimal solution takes several hundred seconds). We also analyze the effect of different thermal parameters, such as the initial temperature, the final temperature and the thermal resistance.

Optimum: Thermal-aware task allocation for heterogeneous many-core devices

2014 International Conference on High Performance Computing & Simulation (HPCS), 2014

Temperature management is a key challenge for many-core platforms in the dark silicon era as all the cores cannot be powered-on together at the maximum frequency and either some cores should run at lower frequency or only a portion can be used without burning the device. In addition, due to process variations and/or design optimization, not all the integrated processing elements (PEs) are identical and each of them may feature a different power/temperature/frequency trade-off. Many works have been proposed to tackle the thermalaware task mapping problem in multicore devices, but none has yet demonstrated the capability to find optimal solutions within seconds for a large number of cores, with heterogeneous power/frequency operating points, while ensuring a safe transient thermal map. In this paper we propose a new Integer Linear Programming formulation, based on a coarse-grain dynamic thermal model, for this class of problems. Our solver finds optimal solutions in few seconds for a 64 core system. Furthermore, we show that by limiting the number of iterations in the solver, we achieve low optimality gaps, with times compatible to an on-line (execution time) use of the optimal allocator.

Efficient Implementation of Thermal-Aware Scheduler on a Quad-core Processor

2011

Due to power wall and slow performance improvement in a single core micro-architecture, multiple even many cores based processors rose as the main stream processor. Nevertheless, thermal threats regarding reliability and lifetime of processors are still among the major concerns which received much attention in terms of algorithms and hardware design to reduce processor temperature and keep application performance in recent years. In this paper, we propose and implement a thermal-aware Round-Robin scheduling algorithm for process migration in the Linux environment on a quad-core processor. Bearing designer's goals in mind, such as performance, load-balancing, and reliability, we managed to achieve much bigger temperature fall than previous results of Round-Robin scheduler on a dual-core processor as well as baseline Linux scheduler on a quad-core processor. Moreover, the performance loss due to scheduling overhead is modest in our approach. Our results indicate that thermal-aware scheduling is a valid approach to tackling thermal issues on multi-core processors. There will be increasing demand for thermal-aware scheduling as the number of cores on a single processor increases.

Thermal aware task sequencing on embedded processors (original) (raw)

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