Model-checking for real-time systems (original) (raw)

Symbolic model checking of real-time systems

Proceedings Eighth International Symposium on Temporal Representation and Reasoning. TIME 2001, 2000

We present a new real-time temporal logic for the specification and verification of discrete quantitative temporal properties. This logic is an extension of the well-known logic CTL. Its semantics is defined on discrete time transition systems which are in turn interpreted in an abstract manner instead of the usual stuttering interpretation. Hence, our approach directly supports abstractions of real-time systems by ignoring irrelevant qualitative properties, but without loosing any quantitative information. We analyse the complexity of the presented model checking algorithm and furthermore present a fragment of the logic that can be efficiently checked.

Analysis of Real-Time Systems with CTL Model Checkers

Electronic Notes in Theoretical Computer Science, 2005

This paper presents a new method for model checking dense real-time systems. The dense realtime system is modeled by a timed automaton and the property is specified with the temporal logic TCTL. Specification of the TCTL property is reduced to CTL and its temporal constraints are captured in a new timed automaton. This timed automaton will be composed with the original timed automaton specifying the real-time system under analysis. Then, the product timed automaton will be abstracted using partition refinement of state space based on strong bi-simulation. The result is an untimed automaton modulo the TCTL property which represents an equivalent finite state system to be model checked using existing CTL model checking tools.

Timed behavior trees and their application to verifying real-time systems

… Conference, 2007. ASWEC …, 2007

Behavior Trees (BTs) are a graphical notation used for formalising functional requirements and have been successfully applied to several case studies. However, the notation currently does not support the concept of time and consequently its application is limited to non-real-time systems.

Temporal logics for real-time system specification

ACM Computing Surveys, 2000

The specification of reactive and real-time systems must be supported by formal, mathematically-founded methods in order to be satisfactory and reliable. Temporal logics have been used to this end for several years. Temporal logics allow the specification of system behavior in terms of logical formulas, including temporal constraints, events, and the relationships between the two. In the last ten years, temporal logics have reached a high degree of expressiveness. Most of the temporal logics proposed in the last few years can be used for specifying reactive systems, although not all are suitable for specifying real-time systems. In this paper we present a series of criteria for assessing the capabilities of temporal logics for the specification, validation, and verification of real-time systems. Among the criteria are the logic's expressiveness, the logic's order, presence of a metric for time, the type of temporal operators, the fundamental time entity, and the structure of time. We examine a selection of temporal logics proposed in the literature. To make the comparison clearer, a set of typical specifications is identified and used with most of the temporal logics considered, thus presenting the reader with a number of real examples.

Formal specification and verification of real-time systems using Graph Grammars

Journal of the Brazilian Computer Society, 2007

This paper presents a formal approach to specify and analyze realtime systems. We extend Object-Based Graph Grammars, a description technique suitable for the specification of asynchronous distributed systems, to be able to explicitly model time constraints. The semantics of the systems is defined in terms of Timed Automata, allowing the automatic verification of properties. Resumo. Este artigo apresenta uma abordagem formal para a especificação e análise de sistemas de tempo real. Gramáticas de Grafos Baseadas em Objetos são extendidas incluindo primitivas para modelar explicitamente restrições de tempo.. A semânticaé definida em termos de autômatos temporais, provendo um método para verificação automática de propriedades.

Time properties verification of UML/MARTE real-time systems

Proceedings of the 2014 IEEE 15th International Conference on Information Reuse and Integration (IEEE IRI 2014), 2014

UML and MARTE are standardized modeling languages widely used in industry for the design of realtime systems. However, formal verification at early phases of the system lifecycle for UML/MARTE models remains an open issue mainly for dependability features. In this paper, we show how we can provide a formal verification of time properties from a UML/MARTE description. For this, we translate this latter description expressed (Timed Computation Tree Logic). We illustrate the proposed approach on a case study derived from a real-time asynchronous system (Integrated Modular Avionics (IMA)-based airborne system).

Analyzing real-time systems

Proceedings of the conference on Design, automation and test in Europe - DATE '00, 2000

Temporal logic model checking is a technique for the automatic verification of systems against specifications. Besides the correctness of safety and liveness properties it is often important to determine critical answer and delay times of systems, especially if they are embedded in a real-time environment. In this paper we present an approach which allows the verification as well as the timing analysis of realtime systems. The systems are described as networks of communicating time-extended finite state machines (I/Ointerval structures). We use a compact symbolic representation to obtain efficient analysis algorithms. 1

Verifying Real-Time Systems with Standard Tools

The TTM/RTTL framework allows for the speciflcation, devel- opment and veriflcation of discrete real-time properties of reactive systems. Timed transition systems (TTMs) is the underlying compu- tational model, and real-time temporal logic (RTTL) is the require- ments speciflcation language. In this paper, we provide a conversion procedure for mapping a timed transition system into a flnite state fair transition systems. This means that eÆcient (untimed) tools for state exploration can be used to check the properties of real-time systems. The procedure has been implemented in the Statetime toolset for the TTM/RTTL framework.

Predicate Diagrams for the Verification of Real-Time Systems

Electronic Notes in Theoretical Computer Science, 2006

We propose a format of predicate diagrams for the verification of real-time systems. We consider systems that are defined as extended timed graphs, a format that combines timed automata and constructs for modeling data, possibly over infinite domains. Predicate diagrams are succinct and intuitive representations of Boolean abstractions. They also represent an interface between deductive tools used to establish the correctness of an abstraction, and model checking tools that can verify behavioral properties of finite-state models. The contribution of this paper is to extend the format of predicate diagrams to timed systems. We also establish a set of verification conditions that are sufficient to prove that a given predicate diagram is a correct abstraction of an extended timed graph. The formalism is supported by a toolkit, and we demonstrate its use at the hand of Fischer's real-time mutualexclusion protocol.