Correct Hardware Design and Verification Methods, 10th IFIP WG 10.5 Advanced Research Working Conference, CHARME '99, Bad Herrenalb, Germany, September 27-29, 1999, Proceedings (original) (raw)

Correct Hardware Design and Verification Methods

Lecture Notes in Computer Science, 2001

This paper investigates specification, verification and test generation for synchronous and asynchronous circuits. The approach is called DILL (Digital Logic in LOTOS). DILL models are discussed for synchronous and asynchronous circuits. Relations for (strong) conformance are defined for verifying a design specification against a high-level specification. An algorithm is also outlined for generating and applying implementation tests based on a specification. Tools have been developed for automated test generation and verification of conformance between an implementation and its specification. The approach is illustrated with various benchmark circuits as case studies.

A design and validation system for asynchronous circuits

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995

In this paper we present a complete methodology for the design and validation of asynchronous circuits starting from a formal specification model that roughly corresponds to a timing diagram. The methodology is presented in such a way that it is easy to embed in the current methodology for synchronous circuits. The different steps of the synthesis process will just be briefly touched upon. The main part of the paper concentrates on the simulation and validation of asynchronous circuits. It discusses where the designer needs validation and how it can be done. It also explains how this process can be automated and embedded in the complete methodology.

A new approach and tool in verifying asynchronous circuits

The 2012 International Conference on Advanced Technologies for Communications, 2012

Research in asynchronous circuit approach has been carried out recently when asynchronous circuits are presented more widely in electronic systems. As they are more important in human life, their correctness should be considered carefully. Although there are some EDA tools for design and synthesis of asynchronous circuits, they are lack of methods for verifying the correctness of the produced circuits. In this work, we are about to propose a verification method and apply it in making a new version of the PAiD tool that can enable engineers to design, synthesize and verify asynchronous circuits. Experiments in verifying circuits have been also provided in this work.

Tools for Validating Asynchronous Circuits

Asynchronous design methodologies can yield designs that are smaller, and/or consume less power, than their synchronous counterparts. Traditional tools, oriented toward synchronous designs, may miss critical asynchronous design problems. This paper describes the modeling methodology and hazard analysis of the SIMIC logic simulator that address asynchronous designs. It also describes XPOWER, an analysis and visualization tool for dynamic power consumption.

Automatic verification of implementations of large circuits against HDL specifications

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1997

This paper addresses the problem of verifying the correctness of gate-level implementations of large synchronous sequential circuits with respect to their higher level specifications in a hardware description language (HDL). The verification strategy is to verify containment of the finite state machine (FSM) represented by the HDL description in the gate-level FSM by computing pairs of compatible states. This formulation of the verification problem dissociates the verification process from the specification of initial states, whose encoding may be unknown or obscured during optimization and also enables verification of reset circuitry. To make verification of large circuits with merged data path and control tractable, the concept of strong containment is introduced. This is a conservative approach which exploits correspondence between data path registers in the two descriptions without requiring any correspondence between the control units. We also present an important result and associated proof that computation of pairs of equivalent or compatible states can be achieved by considering subsets of the circuit outputs. Consequently, verification of circuits with large and diverse input-output sets, which was previously intractable due to lack of a single effective variable order for the binary decision diagrams (BDD's), is now feasible. Experimental results are presented for the verification of several industry level circuits.

Logic design verification via test generation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988

This paper describes a new method for logic design verification in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test patterns, developed to detect single stuck-line faults in the gate-level implementation, are used instead to compare the gate-level implementation with the functional-level specification. In the presence of certain hypothesized design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. It is shown that the class of design errors that can be detected in this way is very large.

An algebraic model for asynchronous circuits verification

IEEE Transactions on Computers, 1988

We present an algebraic methodology allowing us to compare switch-level circuits with higher level specifications. Switch-level networks, "user" behaviors, and input constraints are modeled as asynchronous machines. The model is based on the algebraic theory of characteristic functions (CF). An asynchronous automaton is represented by a pair of CF's, called dynamic CF (DCF): the first CF describes the potential stable states, and the second CF describes the possible transitions. The set of DCF's is a Boolean algebra. Machine composition and internal variables abstraction correspond, respectively, to the product and sum operations of the algebra. Internal variables can be abstracted under the presence of a domain constraint. The constraint is validated by comparison to the outside behavior. The model is well suited for speed-independent circuits for which the specification is given as a collection of properties. Verification reduces to the validation of Boolean inequalities. Index Terms-Abstraction of variables, asynchronous latch, characteristic functions, FIFO queue element, formal verification 3 speed-independent circuit. I. INTRODUCTION ORMAL verification techniques for hardware design are F being developed as an alternative to simulation. Whereas simulation compares results, proofs of correctness involve comparison of functional descriptions. The advantage of formal verification over simulation is that it is a complete method; however, its cost is high computational complexity. Verification must proceed hierarchically, at each level reducing the description complexity by means of abstraction. Numerous theoretical models have been proposed: algebraic methods [27], [16], axiomatic models [23], [25], denotational models using recursive expressions [ 121, [20], predicate logic [I], 1281, [29], and various forms of temporal logic [3], [ll], [211, 1221. The main problem of formal verification are: 1) how to obtain a functional description from the circuit structure, and 2) how to express the high-level specification suitable for comparison. The first problem requires the definition of a formal model, including the specification of primitive elements (axioms), and composition and abstraction laws. Formal verification meth-Manuscript

Validation of Asynchronous Circuit Specifications Using IF/CADP

IFIP International Federation for Information Processing, 2006

This work addresses the analysis and validation of modular CHP specifications for asynchronous circuits, using formalisms and tools coming from the field of distributed software. CHP specifications are translated into an intermediate format (IF) based on communicating extended finite state machines. They are then validated using the IF environment, which provides model checking and bi-simulation tools.

A Correctness Criterion for Asynchronous Circuit Validation and Optimization GANESH GOPALAKRISHNAN

In order to reasonably determine the correctness of asynchronous circuit implementations and specifications, Dill has developed a variant of trace theory [l]. Trace theory describes the behavior of an asynchronous circuit by representing its possible executions as strings, called "traces." A useful relation defined in this theory is called conformance, which holds when one trace specification can be safely substituted for another. We propose a new relation in the context of Dill's trace theory, called strong conformance. We show that this relation is capable of detecting certain errors in asynchronous circuits that cannot be detected through conformance. Strong conformance also helps to justify circuit optimization rules where a component is replaced by another component having extra capabilities (e.g., it can accept more inputs). The structural operators of Dill's trace theory+ompose, rename, and hide-are shown to be monotonic with respect to strong conformance. Experiments are presented using a modified version of Dill's trace theory verifier that implements a check for strong conformance.