On-chip generator of a saw-tooth test stimulus for ADC BIST (original) (raw)
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On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST
Journal of Electronic Testing, 2003
In the context of analog BIST for ADC, this paper presents two structures for the internal generation of a linear signal used with the histogram-based test technique. All of these structures use wide-swing current mirrors and an original adaptive system to make the generators less sensitive to process variations. The first structure allows us to generate high quality ramp signal.
On-chip ramp generators for mixed-signal BIST and ADC self-test
IEEE Journal of Solid-State Circuits, 2003
A practical approach to generate on-chip precise and slow analog ramps, intended for time-domain analog testing, monotonicity and histogram-based tests of ADCs is proposed. The technique uses an analog discrete-time adaptive scheme to calibrate the ramp generator. The lowest slope is 0.4 V/ms. Three implementations are presented for different levels of accuracy and complexity. Measurement results show excellent accuracy and programmability, up to only 0.6% of slope error and maximum integral nonlinearity error of 175 V. Experimental and theoretical results are in good agreement.
Cost effective signal generators for ADC BIST
2009 IEEE International Symposium on Circuits and Systems, 2009
ADC in SOC usually has no connection to the outside. Built-in self-test is a good way to verify this block's performance. Stringent requirement of stimulus generator is the most important limitation of ADC BIST. Several methods of using stimulus with low linearity to test ADC with high linearity have been reported for standalone production test. These methods can be adapted for ADC BIST to reduce the BIST cost overhead. This paper investigates signal patterns that can be used in low cost BIST scheme. Two cost effective stimulus generator structures are presented. Simulation results shows that the generated signal with less than 7 bits linearity can be used to test a 16 bits ADC. The estimation errors of INL are less than 0.65 LSB. I.
Stimulus generator for SEIR method based ADC BIST
Proceedings of the IEEE 2009 National Aerospace & Electronics Conference (NAECON), 2009
Testing of ADC in SOC is a significant challenge since it usually has no connection to the outside. Built-in self-test (BIST) is regarded as a promising alternative to traditional test. Most reported ADC BIST research works try to replicate a production test scheme on chip. This approach requires input ramp with high linearity which is hard to achieve on chip. This paper investigates signal generator implementation issues of adapting stimulus error identification and removal method which was presented for production test into a practical ADC BIST solution. A stimulus generator using very small transistor count is presented. Extremely simple methods for generating small constant voltage level shifts are introduced and evaluated. Simulation results show that generated signals with less than 7 bits linearity, together with the simple level shifts, are able to test a 16-bit ADC to 16 bit accuracy level. These results demonstrate that accurate BIST of deeply embedded AMS blocks may be practically implemented on chip with very low overhead.
IEEE Transactions on Very Large Scale Integration Systems, 2019
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PWM-based test stimuli generation for BIST of high resolution ΣΔ ADCs
2008 Design, Automation and Test in Europe, 2008
A fully digital test stimuli generation and on-chip specifications evaluation for cheap, fast, though accurate testing of high resolution Σ∆ ADCs are here presented. Simulations and measurements showed a discrimination threshold on specification parameters up to-90dBc. The proposed method helps reduce the cost of ADC production test, to extend test coverage and to enable Built-In Self-Test and test-based self-calibration.
BIST and production testing of ADCs using imprecise stimulus
ACM Transactions on Design Automation of Electronic Systems, 2003
A new approach for testing mixed-signal circuits based upon using imprecise stimuli is introduced. Unlike most existing Built-In Self-Test (BIST) and production test approaches that require excitation signals that are at least 3 bits or more linear than the Device-Under-Test (DUT), the proposed approach can work with stimuli that are several bits less linear than the DUT. This dramatically reduces the requirements on stimulus generation for BIST applications and offers potential for using inexpensive signal generators in production test, or for testing DUTs that have a linearity performance exceeding that of the available test equipment. As a proof of concept, a histogram-based algorithm for linearity testing for Analog-to-Digital Converters (ADCs) has been proposed. It can estimate the Integral Nonlinearity (INL) and Differential Nonlinearity (DNL) of an n -bit ADC by using a ramp signal of much less than n -bit linearity and a shifted version of the same nonlinear ramp as excitati...
High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy
IEEE Transactions on Instrumentation and Measurement, 2009
This paper proposes a digital-compatible built-in self-test (BIST) strategy for high-resolution analog-to-digital converter (ADC) linearity testing using only digital testing environments. The on-chip stimulus generator consists of three lowresolution and low-accuracy current steering digital-to-analog converters (DACs), which are area efficient and easy to design. The linearity of the stimuli is improved by the proposed reconfiguration technique. ADCs' outputs are evaluated by simple digital logic circuits to characterize the nonlinearities. The proposed BIST strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. The testing performance is not sensitive to the mismatches and process variations, so that the analog BIST circuits can easily be reused without complex self-calibration. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INL k error of 12-bit ADCs to a ±0.15 least significant bit (LSB) accuracy level using only 7-bit linear DACs.
A low-cost BIST architecture for linear histogram testing of ADCs
This paper investigates the viability of an ADC BIST scheme for implementing the histogram test technique. An original approach is developed to extract the ADC parameters from the histogram with a minimum area overhead. In particular, it is shown that the choice of a triangle-wave input signal combined with an appropriate time decomposition technique of the test procedure permits to drastically reduce the required on-chip hardware circuitry.