HARPO/L: A language for hardware/software codesign (original) (raw)

A software oriented approach to hardware/software codesign

1994

We present a software oriented approach to hardware/software codesign by applying traditional compiler techniques to the hardware/software partitioning problem and linking a compiler to a state of the art hardware synthesis technology. The system is specified in C or C++. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic, connected to a Sparc based workstation via the system bus. We present a novel partitioning technique based on a hierarchical candidate preselection scheme, that utilizes profilers and estimators for performance and cost. Our approach allows (a) efficient collection of profiling data due to the usage of C and C++ as specification languages, (b) fast partitioning due to a candidate preselection scheme, and (c) high complexity of the hardware partition due to a logic emulation system.

A flexible specification framework for hardware-software codesign (poster paper)

Proceedings of the conference on Design, automation and test in Europe, 2000

In this poster, we present a new specification technique for complex hardware-software systems, based on standard high-level programming languages, such as C, C++, Java, Scheme, or Ada, without extensions or semantic changes. Unlike previous approaches, the designer may choose the model of computation and the specification language that best suits her needs, while still being able to formally verify the correctness of the specification. The details of the available hardware and software resources, and the implementation of the different models of computation are encapsulated in libraries to maximize reuse in system specifications.

Leveraging reconfigurability in the hardware/software codesign process

ACM Transactions on Reconfigurable Technology and Systems, 2011

Current technology allows designers to implement complete embedded computing systems on a single FPGA. Using an FPGA as the implementation platform introduces greater flexibility into the design process and allows a new approach to embedded system design. Since there is no cost to reprogramming an FPGA, system performance can be measured on-chip in the runtime environment and the system's architecture can be altered based on an evaluation of the data to meet design requirements.

EDgAR: A Platform for Hardware/Software Codesign

Embedded System Applications, 1997

Codesign is a uni ed methodology to develop complex systems with hardware and software components. EDgAR, a platform for hardware/software codesign is described, which i s i n tended to prototype complex digital systems. It employs programmable logic devices (MACHs and FPGAs) and a transputer-based parallel architecture. This platform and its associated methodology reduce the systems production cost, decreasing the time for the design and the test of the prototypes. The EDgAR supporting tools are introduced, which w ere conceived to specify systems at an high-level of abstraction, with a standard language and to allow a high degree of automation on the synthesis process. This platform was used to emulate an integrated circuit for image processing purposes.

I-Codesign: A Codesign Methodology for Reconfigurable Embedded Systems

2016

Hardware/software codesign involves various design problems including system specification, design space exploration and hardware/software partitioning. An effective codesign process requires accurately predicting the performance, cost and power consequence of any design trade-off in algorithms or hardware characterization. In order to satisfy these design constraints we developed a new codesign methodology: I-codesign. It starts with describing the system specification with probabilistic estimations of the execution scenarios along with real-time and inclusion/exclusion parameters. Then, a three phase partitioning approach is applied to the specification where each phase deals with a specific set of constraints. An embedded controller code is generated at the end of the methodology that acts at run-time on the reconfiguration requests.

Hardware-software codesign of embedded systems

1994

Abstract Designers generally implement embedded controllers for reactive real-time applications as mixed software-hardware systems. In our formal methodology for specifying, modeling, automatically synthesizing, and verifying such systems, design takes place within a unified framework that prejudices neither hardware nor software implementation. After interactive partitioning, this approach automatically synthesizes the entire design, including hardware-software interfaces.

A Logic-Based Approach for Hardware/Software Codesign

2000

In the hardware industry, simulation is still all too frequently considered synonymous with verification. The design process usually consists of developing an implementation from a specification without the use of any formal proof techniques. Both are then simulated for a number of inputs (an approach known as co-simulation [1]). Bugs discovered are removed and the simulation process is repeated over again. However, formal verification cannot completely replace the existing simulation approach.

A codesign back-end approach for embedded system design

ACM Transactions on Design Automation of Electronic Systems, 2000

Continuous advances in processor and ASIC technologies enable the integration of more and more complex embedded systems. Since their implementations generally require the use of heterogeneous resources (e.g., processor cores, ASICs) in one system with stringent design constraints, the importance of hardware/software codesign methodologies increases steadily. Interfacing heterogeneous hardware and software components together through a communication structure is particularly error prone and time consuming. Hence, on the basis of a generic architecture dedicated to telecommunication and multimedia applications, we propose an extended communication synthesis method that provides characterization of communications and their implementation schemes in the target architecture. This method takes place after the partitioning and scheduling phase and may constitute the basis of a back-end of a codesign framework leading to HW/SW integration.