Designing of RF Single Balanced Mixer with a 65nm CMOS Technology Dedicated to Low Power Consumption Wireless Applications (original) (raw)

CMOS Technology Dedicated to Low Power Consumption Wireless Applications

2014

The present work consists of designing a Single Balanced Mixer (SBM) with the 65 nm CMOS technology, this for a 1.9 GHz RF channel, dedicated to wireless applications. This paper shows; the polarization chosen for this structure, models of evaluating parameters of the mixer, then simulation of the circuit in 65nm CMOS technology and comparison with previously treated.

A 65-NM CMOS RF Mixer for Different Applications

2015

A down conversion RF mixer is designed with 65nm CMOS technology for a different low power consumption applications. Mixer structure comprises a double-balanced Gilbert-Cell with improving linearity method in the RF stage of circuit; all is at a supply voltage of 1.8V and a power of 2.17 mW. The circuit is simulated for different spectrum applications as: 200 MHz mobile users, 1.9 GHz wireless applications, and 20 to 60 GHz commercial satellite and pointtopoint communications. The reported design achieves good values in terms of a radio frequency mixer evaluating parameters such as: Consumed Power, Conversion Gain, Noise Figure and Linearity.

High linearity, low power RF mixer design in 65nm CMOS technology

AEU - International Journal of Electronics and Communications, 2014

A design of RF down-conversion Gilbert-Cell, with 65 nm CMOS technology, at a supply voltage of 1.8 V, with a new degenerating structure to improve linearity. This architecture opens the way to more integrated CMOS RF circuits and to achieve a good characteristics in terms of evaluating parameters of RF mixers with a very low power consumption (2.17 mW). At 1.9 GHz RF frequency; obtained results show a third order input intercept point (IIP3) equal to 11.6 dBm, Noise Figure (NF) is 4.12 dB, when conversion gain is 8.75 dB.

A Wideband Single-balanced Down-mixer for the 60 GHz Band in 65 nm CMOS

HAL (Le Centre pour la Communication Scientifique Directe), 2010

This paper presents a single-balanced direct down conversion mixer for the unlicensed 60 GHz band. It is based on a differential pair employing the current bleeding technique. An integrated 60 GHz wideband passive balun allows the use of a single ended local oscillator (LO). The circuit is fabricated using the 65 nm bulk CMOS technology of ST Microelectronics. The mixer's baseband reaches from DC to 2 GHz. The measured radio frequency (RF) bandwidth exceeds 11 GHz, ranging from 54 GHz to at least 65 GHz. The measured RF, IF (intermediate frequency) and LO port return losses lie below -20 dB, -15 dB and -10 dB, respectively, within this entire band. A maximum conversion gain of 9.1 dB at 100 MHz from the carrier is achieved, while typical values measured at 1 GHz IF lie around 6 dB throughout the entire band. The mixer delivers these optimum results for LO powers as low as -5 dBm. The output referred 1 dB compression point reaches -5 dBm for -1 dBm of LO power. The simulated single sideband (SSB) noise figure is of 9 dB. Including the differential IF buffer that can drive two singleended 50 Ω loads, the circuit draws 16.8 mA from a 1 V supply. The pad-limited die size is only 0.52 x 0.49 mm 2 .

Monolithic RF active mixer design

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1999

An overview of monolithic radio-frequency (RF) active mixer design is presented. The paper is divided into two parts. The first part discusses the performance parameters that are relevant to the design of downconversion mixers, and how they affect the system performance. The second part presents three common kinds of mixer topologies, namely, unbalanced, singlebalanced, and double-balanced designs. This paper concentrates on active mixers only. The advantages and disadvantages, as well as the design and optimization techniques for the three kinds of mixers, are discussed.

Linearity improvement in a CMOS down-conversion active mixer for WLAN applications

Analog Integrated Circuits and Signal Processing, 2019

This paper presents an active down-conversion mixer for wireless local area network applications. The proposed downconversion mixer is designed for 2-3 GHz radio frequency (RF) band and an intermediate frequency of 100 MHz using RF-TSMC CMOS 0.18 lm technology. A new fully differential Darlington cell is introduced in the RF transconductance stage to effectively suppress third-order nonlinearity. In addition, the conversion gain and noise performance of the proposed mixer are improved by using an active load and current bleeding technique. The proposed mixer has been simulated by Cadence Spectre-RF. Post-layout simulation results show the third-order input intercept point can be improved up to 12.5 dBm by optimum biasing of the Darlington cell. The proposed mixer achieves the high conversion gain of 14.5 dB and the low double side-band noise figure of 4.55 dB at the input frequency of 2.4 GHz. The mixer operates at the supply voltage of 1.8 V with power consumption of 17.4 mW.

Fundamental performance limits and scaling of a CMOS passive double-balanced mixer

2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, 2008

In this paper, fundamental performance limits and scaling of a double-balanced passive mixer are examined. Analysis of the passive double-balanced mixer will show how its performance metrics are directly affected by the down-scaling of the transistor gate length, L G. We analyze the performance in terms of conversion gain (G C), 1-dB compression point (P 1-dB) which we derive, and SSB Noise Figure (NF). We will show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance. This is verified through simulation and modeling results for mixers designed in CMOS 350nm to 32nm technology. We introduce a mixer's figure-of-merit (FOM MIXER) to compare performance with technology scaling. Circuit designers and System architects can use this paper to find a suitable process technology that will meet their specifications. I.

A 9–31-GHz Subharmonic Passive Mixer in 90-nm CMOS Technology

IEEE Journal of Solid-State Circuits, 2006

A subharmonic down-conversion passive mixer is designed and fabricated in a 90-nm CMOS technology. It utilizes a single active device and operates in the LO source-pumped mode, i.e., the LO signal is applied to the source and the RF signal to the gate. When driven by an LO signal whose frequency is only half of the fundamental mixer, the mixer exhibits a conversion loss as low as 8-11 dB over a wide RF frequency range of 9-31 GHz. This performance is superior to the mixer operating in the gate-pumped mode where the mixer shows a conversion loss of 12-15 dB over an RF frequency range of 6.5-20 GHz. Moreover, this mixer can also operate with an LO signal whose frequency is only 1/3 of the fundamental one, and achieves a conversion loss of 12-15 dB within an RF frequency range of 12-33 GHz. The IF signal is always extracted from the drain via a low-pass filter which supports an IF frequency range from DC to 2 GHz. These results, for the first time, demonstrate the feasibility of implementation of high-frequency wideband subharmonic passive mixers in a low-cost CMOS technology.