A 3-D packaging concept for cost effective packaging of MEMS and ASIC on wafer level (original) (raw)
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2008 58th Electronic Components and Technology Conference, 2008
Stacking of wafers with low chip-yield and non uniform chips size is developed for MEMS and 3D packaging applications. Stacking of MEMS and ASIC wafers one over other is difficult due to difference in chip yield and chip size. A cap wafer which is used for sealing the MEMS wafer in the wafer level package (WLP) is used for stacking the known good dice from MEMS wafer. Cavities and through silicon vias (TSV) are formed on a support wafer which matches with the ASIC (Electronics) wafer. Based on the mapping of the ASIC wafer, a known good die from MEMS wafer is picked and attached into the support wafer. MEMS devices are attached in to the support wafer either by face down or face up with respect to ASIC chip. Redistribution lay outs are made on the ASIC wafer to match the pads configuration of the MEMS and ASIC wafer. The completed support wafer with MEMS devices in the cavity is bonded with ASIC wafer in a wafer bonder for final assembly. Since through hole vias are formed on the support wafer there is no need to etch through silicon via on either MEMS or AISC wafer. A hermetically sealed MEMS chip with ASIC one over other is assembled to meet the final real estate reduction of the package size. A stacking approach for low yield and non uniform chip size wafers is demonstrated.
Wafer-level thin-film encapsulation for MEMS
Microelectronic Engineering, 2009
The diversity and complexity of many microelectromechanical systems (MEMS), combined with the mechanical nature of the devices involved, means that the handling, dicing and packaging of these structures can pose many problems. So-called 'zero-level' packaging options are now often used to protect the devices at the wafer scale before the wafer is diced and sent for conventional packaging. This paper describes a novel process flow for the fabrication of integrated MEMS thin-film packages within a lowtemperature, CMOS-compatible process. A double sacrificial layer is used, which encapsulates the device of interest within a shell of silicon oxide. The sacrificial layer is then removed through lateral etch channels and the shell is sealed. The technique requires minimal extra wafer space, allows the use of low-temperature materials within the process flow, and the novel channel design means that the shell may be easily sealed. Preliminary visual and electromechanical tests using simple fixed-fixed beam test structures indicate that the package is sealed, the device is undamaged and that encapsulation has little or no effect on device performance.
Design and development of a multi-die embedded micro wafer level package
2008
The primary trend in electronics industry is product miniaturization. Both design and manufacturing engineers are looking for ways to make products lighter, smaller, less expensive, and at the same time faster, more powerful, reliable, user-friendly, and functional. A partial list of today's "shrinking" products would include cellular phones, personal and sub-notebook computers, pagers, PCMCIA cards, camcorders, palmtop organizers, telecommunications equipment, and automotive components. With silicon chips continue integrating more functionality as per Moore's Law, the packaging is challenged to integrate and shrink. Chips First or Embedded Chip packaging is a revolutionary way to overcome these recent packaging integration challenges. Packaging researchers have worked on embedded packaging and developed newer way of embedding the chip. The PBGA replaced the lead frame based peripheral array packages, in which the die is electrically connected to circuit board (PCB) substrate by wire bonding or flip chip technology, before covering with molding compound. Embedded Wafer level packaging takes the next step, eliminating the PCB, as well as the need to use wire bonding or flip-chip bumps to establish electrical connection. This paper deals with the development embedding multiple dies at wafer level.
Technology Requirements for Chip-On-Chip Packaging Solutions
Proceedings Electronic Components and Technology, 2005. ECTC '05., 2005
The trend towards smaller, lighter and thinner products requires a steady miniaturization which has brought-up the concept of Chip Scale Packaging (CSP). The next step to reduce packaging cost was the chip packaging directly on the wafer. Wafer Level Packaging (WLP) enables the FC assembly on PWB without interposers. New and improved microelectronic systems require significant more complex devices which could limit the performance due to the wiring of the subsystems on the board. 3-D packaging using the existing WLP infrastructure is one of the most promising approaches. Stacking of chips for chip-on-chip packages can be done by wafer-to-wafer stacking or by chip-to-wafer stacking which is preferable for yield and die size considerations. This chip-on-chip packaging requires a base die with redistribution traces to match the I/O layout of both dice. This allows the combination of the performance advantage of flip chip with the options of WLP. To avoid the flip chip bonding process the thin chip integration (TCI) concept can be used. Key elements of this approach are extremely thin ICs (down to 20 µm thickness) which are incorporated into the redistribution. This technology offers excellent electrical properties of the whole microelectronic system. The focus of this paper will be the technology requirements for the realization of different kinds of chip-onchip packages.
A modular and generic monolithic integrated MEMS fabrication process
Superficies y Vacío, 2017
A modular and generic, monolithic integrated MEMS fabrication process is presented to integrate microelectronics (CMOS) with mechanical microstructures (MEMS). The proposed monolithic integrated fabrication process is designed using an intra-CMOS approach (to fabricate the mechanical microstructures into trenches without the need of planarization techniques) and a CMOS module (to fabricate the electronic devices) with a 3 ?m length as minimum feature. The microstructures module is made up to three polysilicon layers, and aluminum as electrical interconnecting material. From simulation results, using the SILVACO® suite (Athena and Atlas frameworks), no significant degradation on the CMOS performance devices was observed after MEMS manufacturing stage; however, the thermal budget of the modules plays a crucial role, because it set the conditions for obtaining the complete set of devices fabricated near their optimal point. Finally, to evaluate and to support the development of the pro...
2011
Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional stacking of thin dies is demonstrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm × 10 mm × 0.4 mm and solder ball pitch of 0.4 mm. As part of the development several key processes like thin die stacking, 8-in wafer encapsulation using compression molding, low-temperature dielectric with processing temperature less than 200°C have been developed. The EMWLP components success fully pass 1000 air to air thermal cycling (-40°C to 125°C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (>; 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q-factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL, and package thicknesses can lead to designs with improved mechanical reliability.
This paper highlights a number of challenges and solutions developed to meet the needs of MEMS manufacturers using 3D packaging for low I/O count devices. Various process steps, such as, TSV etch, dielectric liner deposition, barrier/seed PVD have been developed and optimized to increase electrical performance, increase throughput and reduce costs for volume production. In particular, various silicon etch processes have been developed to create a wide range of TSV profiles, both tapered (allowing relatively simple deposition processes) and vertical (reducing real estate). Unique endpointing techniques have also been proven in production for both tapered and vertical vias. Low temperature PECVD is also a key process, for depositing via dielectrics onto bonded wafers with a low temperature (<200°C) threshold. Finally, this paper illustrates some of the challenges regarding barrier/seed deposition using conventional PVD, and ionized PVD and how technologies such as MOCVD may be useful.
High Yield Polymer MEMS Process for CMOS/MEMS Integration
MRS Proceedings, 2011
ABSTRACTMEMS community is increasingly using SU-8 as a structural material because it is self-patternable, compliant and needs a low thermal budget. While the exposed layers act as the structural layers, the unexposed SU-8 layers can act as the sacrificial layers, thus making it similar to a surface micromachining process. A sequence of exposed and unexposed SU-8 layers should lead to the development of a SU-8 based MEMS chip integrated with a pre-processed CMOS wafer. A process consisting of optical lithography to obtain SU-8 structures on a CMOS wafer is described in this paper.
New Packaging and Interconnect Technologies for Ultra Thin Chips
2010
This paper shows different approaches to use the availability of ultrathin chips for the realization of new packages with high density and improved performance. For several years technologies have been developed for the embedding of chips in circuit boards in order to achieve 3D-packages using conventional processes from PCB manufacturing. Ultrathin chips are suited to be integrated in rigid circuit boards as well as on and in multilayer flexible substrates. The use of interposers prior to embedding can facilitate the embedding of components with ultra fine pitches. An example for a complex RFID-based product will be shown which is enabled by the integration of ultrathin dies. INTRODUCTION A visionary approach for the future production of printed circuit boards was the development of integration technologies for active and passive components in the different layers of the boards. This enables extremely high density of functionality and components in 3 dimensions. The goal is to achi...
Module miniaturization by ultra thin package stacking
2010
The scope of the European project TIPS (Thin Interconnected Package Stacks) is the fabrication of ultra thin packages for electronic components and the subsequent stacking and interconnection of those packages to form highly compact modules. In the first part of this paper approaches to fabricate ultra thin 10 × 10 mm packages by embedding technologies for chips into printed circuit board environments will be discussed. One technology uses commercial flexible printed circuit board substrates (polyimide sandwiched in Cu layers) and respective fabrication processes. After initial patterning of the Cu the chips are die bonded to the flex substrates and subsequently laminated into build up layers. Electrical contact between the chip and a fan out routing on the outer layer of the package are made by micro via formation, electroplating and wet chemical structuring of the metal layers. The thickness of the embedded components is constricted to 50 μm in order to constrain the package thicknesses to a maximum of 100 μm with this approach. The alternative approach, the ultra thin chip package (UTCP) technology, aims at package thicknesses around 60 μm. In this case 20 μm thick chips are die-bonded to thin polyimide layer. A photo-definable polyimide is then applied over the assembled chips by spin-on technique. Contact pads are opened by exposure and development of the polyimide, followed by metal sputtering, electroplating and etching. In this approach the thickness of embedded components is typically 20-30 μm and final package thickness is in the range of 60 μm. In both approaches the packages are fabricated as batches consisting of 150 × 150 mm sheets of flex substrates. Stacking of individual packages can be performed in an automated package by package placement process using a frame as alignment tool and typical flexible printed circuit boards adhesives. In this way only known-good-packages are stacked in o- - rder to minimize yield loss. However, a more straight forward process is stacking of the packages using fabrication batches and established multilayer printed circuit board technologies. The disadvantage is the potential yield loss if one of the packages in a stacked layer is faulty. For either type of stacking process the individual stacks have to be milled out of the stack fabrication batch. Development issues, design considerations and results of first fabrication runs will be presented and discussed.