Practical methodology for analyzing the effect of conductor roughness on signal losses and dispersion in interconnects (original) (raw)
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Roughness characterization for interconnect analysis
2011
A novel method for practical prediction of interconnect conductor surface roughness effect on multi-gigabit digital signals is proposed. A differential impedance operator of a conductor is constructed with Trefftz finite elements and locally adjusted with a correction coefficient to account for the roughness effect. Any correction coefficient derived for the additional power loss due to roughness can be used with the proposed method. Modified Hammerstad's correction coefficient is proposed and used here as an example. A test board is manufactured and investigated up to 50 GHz. Parameters of the conductor roughness model are identified with generalized modal S-parameters. An increase of effective dielectric constant due to conductor surface roughness is observed and explained by capacitive effect of spikes on the surface of conductor. It is shown that the constructed interconnect models are consistent with the measured data.
Meaningful interconnect design and compliance analysis must start with the identification of broadband dielectric and conductor roughness models. Such models are not available from manufacturers and the model identification is the most important element of successful interconnect design for link paths with 10-50 Gbps and higher data rates. Electromagnetic analysis of interconnects without such models may be simply not accurate. Overview of broadband dielectric and conductor roughness models for PCB and packaging interconnect problems is provided in the paper. Theory of model identification with generalized modal S-parameters and separation of dielectric and conductor dispersion and loss effects is described. Practical examples of successful dielectric and conductor roughness model identification up to 50 GHz are also provided.
Unified approach to interconnect conductor surface roughness modelling
2017 IEEE 26th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS), 2017
Commonalities of five conductor roughness models are analysed and unified form of roughness correction coefficient (RCC) is suggested in the paper. It is shown that Hammerstad, Huray, Groiss, Hemispherical and Bushminskiy roughness correction coefficients can be written in the following unified form K=1+(RF-1)∗F(SR), where RF is roughness factor that has meaning of maximal possible increase of losses with frequency due to the conductor roughness. F is a frequency-dependent function describing transition from zero at lower frequencies to one at higher frequencies (roughness transition function). It is shown that the unified RCC can be used in multi-level additive form for surfaces with two or more dominant discontinuity sizes or in multi-level multiplicative form for surfaces with fractal type discontinuities. Measurements on a test board are used to identify and compare all five RCCs.
Analytical Model for Optimum Signal Integrity in PCB Interconnects Using Ground Tracks
IEEE Transactions on Electromagnetic Compatibility, 2009
In this paper, we present analytical models for line impedance and the coupling coefficient in the presence of additional ground tracks. We use a variational analysis combined with the transverse transmission-line technique to model interconnect lines guarded by ground tracks. Using the proposed model, it would be possible for designers to reduce crosstalk in coupled lines and obtain desired line impedance, thereby ensuring optimum signal integrity. The results obtained are verified by full-wave simulations and measurements performed on a vector network analyzer. The proposed model may find applications in the design and analysis of high-speed interconnects. Index Terms-Crosstalk, finite-difference time-domain (FDTD), ground tracks, printed circuit board (PCB) interconnects, signal integrity, variational analysis. 0018-9375/$25.00 © 2009 IEEE Rohit Sharma (M'08) received the B.E. degree in electronics and telecommunication engineering from North Maharashtra University, Jalgaon, India, and the M.Tech. degree in systems engineering from Dayalbagh Educational Institute, Agra, in 2000 and 2003, respectively. He is currently working toward the Ph.D. degree on high-speed interconnect modeling at the Jaypee University of Information Technology, Solan, India.
Systematic development of transmission-line models for interconnects with frequency-dependent losses
IEEE Transactions on Microwave Theory and Techniques, 2001
This paper presents a new method for the extraction of the frequency-dependent, per-unit-length (p.u.l.) resistance, and inductance parameters of multiconductor interconnects. The proposed extraction methodology is based on a new formulation of the magneto-quasi-static problem that allows lossy ground planes of finite thickness to be modeled rigorously. The formulation is such that the p.u.l. impedance matrix for the multiconductor interconnect is extracted directly at a prescribed frequency. Once the matrix has been calculated over the bandwidth of interest, rational function representations of its elements are generated through a robust matrix curve-fitting process. Such a formulation enables subsequent transient analysis of interconnects through a variety of approaches. Direct incorporation of the rational function model into a general-purpose circuit simulator and a standalone multiconductor-transmission-line simulator is demonstrated.
Simulation of frequency dependent conductor loss in interconnects
1996
Simulation of frequency dependence of conductor losses is important for getting accurate electrical performance data of interconnects. The method of characteristics is extended to take into account this effect. The method is well suited for incorporating into a general purpose circuit analysis program for time domain simulation. This enables the analysis of interconnects connected in any arbitrary topology along with the associated nonlinear circuits for high speed digital and analog systems
IEEE Transactions on Electromagnetic Compatibility, 2000
Copper foil in printed circuit board (PCB) transmission lines/interconnects is roughened to promote adhesion to dielectric substrates. It is important to characterize PCB substrate dielectrics and correctly separate dielectric and conductor losses, especially as data rates in high-speed digital designs increase. Herein, a differential method is proposed for separating conductor and dielectric losses in PCBs with rough conductors. This approach requires at least three transmission lines with identical, or at least as close as technologically possible, basic geometry parameters of signal trace, distance-to-ground planes, and dielectric properties, while the average peak-to-valley amplitude of surface roughness of the conductor would be different. The peak-to-valley amplitude of conductor roughness is determined from scanning electron microscopy images.
Application of system-level EM modeling to high-speed digital IC packages and PCBs
IEEE Transactions on Microwave Theory and Techniques, 1997
A system-level electromagnetic (EM) modeling tool combining a three-dimensional (3-D) full-wave finite-element EMfield analysis tool and a time-domain electric-circuit simulator is developed and applied to various geometries such as multilayer printed circuit boards (PCB's), signal lines embedded in a PCB or package, and split power-distribution network. Since the signal integrity is a primary concern of high-speed digital circuits, the noise distributions on various circuit planes are evaluated from the analysis. These noise distributions, often called noice maps, are utilized to identify the location of the major source of simultaneous switching noise (SSN). This information can eventually be adapted for optimum placement of decoupling capacitors to minimize the noise fluctuations on the various circuit planes on an entire PCB. area of EM design and characterization of microwave/millimeter-wave circuits and components and VLSI and MMIC interconnects using the FEM, and development of numerical techniques for analysis and design of high-speed high-frequency circuits with emphasis on parallel/super computing.
Signal integrity loss in bus lines due to open shielding defects
The Eighth IEEE European Test Workshop, 2003. Proceedings., 2003
Interconnect structures in high speed circuits play an important role in present CMOS technologies. Inductance and capacitance coupling effects (crosstalk) may cause a significant loss in signal integrity in high performance systems. One way to reduce these effects is to place a signal line between two grounded lines (shield). In this paper we study the influence of defective grounding of shielding lines.
Modeling frequency-dependent conductor losses and dispersion in serial data channel interconnects
2007
Models of transmission lines and transitions accurate over 5-6 frequency decades are required to simulate interconnects for multi-gigabit serial data channels. Extremely broadband modeling of conductor properties for such high-speed channels is a particularly challenging task for electromagnetic tools. This paper discusses the conductor effects in general and the approximations used in different simulation technologies and tools.