Formal verification of SoC based embedded design using context based assertions (original) (raw)
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Model Checking as the predominant technique for automatically verifying circuits su ers from the well-known state explosion problem. This hinders the veri cation of circuits which contain non-trivial data paths. Recently, it has been shown that for those circuits it may be useful to separate the control and data part prior to veri cation. This paper is also based on this idea and presents an approach for combining various proof approaches like model checking and theorem proving in a unifying framework. In contrast to other approaches, special proof procedures are available to verify circuits with data sensitive controllers, where a bidirectional signal ow between controller and data path can be found. Generic circuits can be veri ed by induction or by model checking nite instantiations. By giving the system`proof hints', also the veri cation e ort for model checking based proofs can be considerably reduced in many cases. The paper presents an introduction to the di erent proof strategies as well as an algorithm for their combination. The underlying C@S system also allows the e ciency evaluation of di erent approaches to verify the same circuits. This is shown in di erent case studies, demonstrating the tradeo between interaction and veri able circuit size.
A Symbolic Modelling Approach for the Formal Verification of Integrated Mixed-Mode Systems
In this paper, a symbolic modelling approach is presented for the formal representation and verification of mixed analog/digital systems. The proposed modelling technique can be incorporated in the SFG-Tracing - a pragmatic methodology originally aimed at the formal verification of digital (VLSI) designs. Existing symbolic analysis and reasoning techniques can be employed to analyse the digital subsystems of a mixed analog/digital design. The development of appropriate, symbolic models to express the functional behaviour of the individual analog components, ultimately enables us to exploit a symbolic evaluation or simulation tool to formally verify the overall functional behaviour of a mixed-mode system.
Functional and formal verification are im- portant methodologies for complex mixed-signal de- signs. But there exist a verification gap between the analog and digital blocks of a mixed-signal system. Our approach improves the verification process by creating mixed-signal assertions which is described by a junction of digital assertions and analog properties. The pro- posed method is a new assertion-based verification flow for designing mixed-signal circuits. The effectiveness of the approach is demonstrated on a �/�-converter.
Functional verification of system on chips-practices, issues and challenges
2002
System on Chip (SoC) designs inherit all the well known verification and validation difficulties associated with complex ASIC designs, besides adding their own set of newer problems. These arise because SoCs are primarily implemented by re-using Intellectual Property (IP) cores. It is well known that verification today constitutes about 70% to 80% of the total design effort, thereby, making it the most expensive component in terms of cost and time, in the entire design flow. It is expected to get even worse for SoC designs.
Formal Verification of Analog and Mixed Signal Designs: Survey and Comparison
2006 IEEE North-East Workshop on Circuits and Systems, 2006
Analog and mixed signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time. In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches.
Introduction to Formal Hardware Verification
1999
Formal hardware veri cation has recently attracted considerable interest. The need for \correct" designs in safety-critical applications, coupled with the major cost associated with products delivered late, are two of the main factors behind this. In addition, as the complexity o f t h e designs increase, an ever smaller percentage of the possible behaviors of the designs will be simulated. Hence, the con dence in the designs obtained by s i m ulation is rapidly diminishing. This paper provides an introduction to the topic by describing three of the main approaches to formal hardware veri cation: theorem-proving, model checking, and symbolic simulation. We outline the underlying theory behind each approach, we illustrate the approaches by applying them to simple examples, and we discuss their strengths and weaknesses. We conclude the paper by describing current on-going work on combining the approaches to achieve m ulti-level veri cation approaches.
A Survey on Assertion-based Hardware Verification
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Hardware verification of modern electronic systems has been identified as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware verification is to drastically reduce the validation and debug time without sacrificing the design quality. Assertion-based verification is a promising avenue for efficient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware verification. Specifically, we outline how to define assertions using temporal logic to specify expected behaviors in different abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hy...
A static verification approach for architectural integration of mixed-signal integrated circuits
Integration, the VLSI Journal, 2010
In this paper we present a static method for verifying the proper integration of analog and mixed signal macro blocks into an integrated circuit. We consider the problem in a setting where there is no golden reference for verifying the validity of the interconnections between the blocks. The proposed verification methodology relies on an abstract modeling of the functional behavior of the blocks and a set of consistency criteria defined over the composition of these abstract models. A new formalism called Mode Sequence Chart (MSeqC) has been presented for capturing the behavior of the blocks at a level of abstraction that is suitable for interconnection verification. We present rules to compose the MSeqCs of each block in an integrated design and present three criteria that indicate possible interconnection faults. We present a tool called AMS-IV (AMS-interconnection verification) that takes the design netlist as input, the MSeqC model of each design block as reference, and tests the three criteria.
Formal verification of analog and mixed signal designs: A survey
Microelectronics Journal, 2008
Analog and mixed signal (AMS) designs are an important part of embedded systems that link digital designs to the analog world. Due to challenges associated with its verification process, AMS designs require a considerable portion of the total design cycle time. In contrast to digital designs, the verification of AMS systems is a challenging task that requires lots of expertise and deep understanding of their behavior. Researchers started lately studying the applicability of formal methods for the verification of AMS systems as a way to tackle the limitations of conventional verification methods like simulation. This paper surveys research activities in the formal verification of AMS designs as well as compares the different proposed approaches.
Formal verification in hardware design
ACM Transactions on Design Automation of Electronic Systems, 1999
In recent years, formal methods have emerged as an alternative approach to ensuring the quality and correctness of hardware designs, overcoming some of the limitations of traditional validation techniques such as simulation and testing.There are two main aspects to the application of formal methods in a design process: the formal framework used to specify desired properties of a design and the verification techniques and tools used to reason about the relationship between a specification and a corresponding implementation. We survey a variety of frameworks and techniques proposed in the literature and applied to actual designs. The specification frameworks we describe include temporal logics, predicate logic, abstraction and refinement, as well as containment between ω-regular languages. The verification techniques presented include model checking, automata-theoretic techniques, automated theorem proving, and approaches that integrate the above methods.In order to provide insight in...