50 V All-PMOS Charge Pumps Using Low-Voltage Capacitors (original) (raw)
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All-pMOS 50-V Charge Pumps Using Low-Voltage Capacitors
IEEE Transactions on Industrial Electronics, 2000
In this work, two high-voltage charge pumps are introduced. In order to minimize the area of the pumping capacitors, which dominates the overall area of the charge pump, high density capacitors have been utilized. Nonetheless, these high density capacitors suffer from low breakdown voltage which is not compatible with the targeted high voltage application. To circumvent the breakdown limitation, a special clocking scheme is used to limit the maximum voltage across any pumping capacitor. The two charge pump circuits were fabricated in a 0.6µm CMOS technology with poly0-poly1 capacitors. The output voltage of the two charge pumps reached 42.8V and 51V while the voltage across any capacitor did not exceed the value of the input voltage. Compared to other designs reported in the literature, the proposed charge pump provides the highest output voltage which makes it more suitable for tuning MEMS devices. Index Terms-Charge pump, high voltage, MEMS interface, polarization voltage, DC-DC converters I. INTRODUCTION D ESPITE the continuous demand for reducing the supply voltage and the power consumption of integrated circuits [1, 2], there are some applications that still require high voltage operation, such as MEMS devices, EEPROM programmers [3-8], power switches [9], LCD and line drivers [10]. To meet the high voltage requirement, capacitive charge pumps are used in light load applications, while step-up DC-DC converters are used in heavy load applications [11-17]. Most of charge pump (CP) topologies in the literature [2, 18-20] are based on the Dickson charge pump [21], which is shown in Fig. 1, where the output voltage is given by: V OU T = (N + 1)V IN − V t1 − V t2 − • • • − V tN − V to (1) where N is the number of stages, V IN is the input voltage, and V ti and V to are the threshold voltages of the i th stage (where i = 1, 2, • • • , N) and the output stage, respectively. This architecture suffers from the continuous increase in the threshold voltage from stage to stage due to the increase in the bulk-source voltage of M i transistor as i increases. Furthermore, the maximum attainable output voltage is limited by
A CMOS charge pump for low voltage operation
2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353), 2000
This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump utilises the cross-connected NMOS, voltage doubler, as a pumping stage. For low-voltage operation, where the performance of the NMOS is limited due to body effect, PMOS are used to increase the pumping gain. Simulations at 50 MHz have shown that for power supply voltages of 2V, 1.5V, 1.2V and 0.9V an output voltage of I1.5V, 8.4V, 6.5V and 4V can be generated respectively, using five pumping stages.
High voltage charge pump using standard CMOS technology
The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004., 2004
An integrated high voltage charge pump circuit utilising intrinsic process features is introduced. It can produce +20V to +50V output from a typical 5V input. The reported charge pumps achieved the highest density and highest output voltages of the industry. Measurements show output ripples of 400mV for frequencies around 10MHz and output load of 28pF. The reported integrated high voltage charge pump circuits was implemented on 0.8µm DALSA Semiconductor technology using standard CMOS devices.
Charge Pump Circuits for Low-voltage Applications
VLSI Design, 2002
In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed. Its pumping operation is based on cascading several crossconnected NMOS voltage doubler stages. For very low-voltage applications (1.2 V, 0.9 V), where the performance of the NMOS transistors is limited due to body effect, two improved versions of the charge pump with cascaded voltage doublers (charge pump with CVD) are also proposed. The first utilises PMOS transistors (charge pump with CVD-PMOS) in parallel to the cross-connected NMOS transistors, while the second improves the pumping gain by boosting the clock amplitude (charge pump with CVD-BCLK). Simulations at 50 MHz have shown that a five-stages charge pump with CVD can achieve a 1.5-8.4 V voltage conversion. For the same stage number and frequency, an output voltage of 4 and 7.3 V can be generated from 0.9 V, by using the charge pump with CVD-PMOS and the charge pump with CVD-BCLK, respectively.
DESIGN, IMPLEMENTATION AND COMPARISON OF VARIOUS CMOS CHARGE PUMPS
A charge pump is a kind of DC to DC converter that uses capacitors as energy storage elements to create a higher or lower voltage power source. Charge pumps make use of switching devices for controlling the connection of voltage to the capacitor. The use of charge transfer switches (CTSs) can improve the voltage pumping gain. Applying dynamic control to the CTSs can reduce reverse currents. This paper includes voltage and power analysis of various charge pump circuits. And a comparison is drawn between the three charge pumps analyzed.
Novel CMOS Bulk-driven Charge Pump for Ultra Low Input Voltage
Radioengineering, 2016
In this paper, a novel bulk-driven cross-coupled charge pump designed in standard 90 nm CMOS technology is presented. The proposed charge pump is based on a dynamic threshold voltage inverter and is suitable for integrated ultra-low voltage converters. Due to a latchup risk, bulkdriven charge pumps can safely be used only in low-voltage applications. For the input voltage below 200 mV and output current of 1 µA, the proposed bulk-driven topology can achieve about 10 % higher efficiency than the conventional gate-driven cross-coupled charge pump. Therefore, it can be effectively used in DC-DC converters, which are the basic building blocks of on-chip energy harvesting systems with ultra-low supply voltage.
Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications
Electronics
Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the cha...
Power efficient charge pump in deep submicron standard cmos technology
IEEE Journal of Solid-State Circuits, 2003
A power efficient charge pump is proposed. The use of low voltage transistors and of a simple 2-phase clocking scheme allows the use of higher frequencies compared to conventional solutions, thus obtaining high current, high efficiency and small area. Measurements show good results for frequencies around 100MHz.
Design and Analysis of Low Power CMOS Charge Pump Circuits For Phase-Locked Loop
2015
A new high efficiency charge pump circuit is designed and realized in 130nm CMOS process. This paper work analyses the design of various CMOS Charge pumps. The performance of charge pumps mainly depends on the ability to efficiently generate high output voltages from the low input supply voltage. The shoot through current and the switching noise are being reduced by the proposed CMOS charge pump circuit. It is also used to improve the large driving capability and for eliminating the reversion loss. The proposed cross coupled charge pump has provided up to 8% percentage efficiency as compared with the conventional CMOS charge pump. The CMOS charge pump (CP) is an integral part in the phase-locked loops. CMOS charge pump circuits used for generating a high voltage from a low supply voltage are used in ICs, such as flash memories, smart power, dynamic random access memories (DRAMs), LEDs and LCD drivers(7). A charge pump is used in DRAMs to generate word-line voltage higher than the su...
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015
this paper describes the implementation of a highoutput current charge pump with passive level shifters, aiming the reliable driving of internal active switches. The technique described here enables advantageous use of high-density integrated Metal-Insulator-Metal (MIM) capacitors with low breakdown voltage, and active switches (MOS transistors). This enables to obtain high power density integration. In addition, capacitor area optimization and feedback control allowing generate constant output voltage are discussed. The 10MHz charge pump was integrated in 0.13µm CMOS process. Thanks to extra epitaxial trench isolation, 18V output voltage with the output current ranging up to 280µA is reached. The target application is the quadrature/frequency compensation of a 3axis vibratory MEMS Gyroscope.