L0TP+: the Upgrade of the NA62 Level-0 Trigger Processor (original) (raw)

The FPGA based Trigger and Data Acquisition system for the CERN NA62 experiment

J. Pinzino, Stefano Venditti, Riccardo Fantechi, Elena Pedreschi

Journal of Instrumentation, 2014

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Progress report on the online processing upgrade at the NA62 experiment

Francesco Simula

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GPUs for fast triggering and pattern matching at the CERN experiment NA62

MARCO STANISLAO SOZZI

2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC), 2009

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herve chanal

Real Time, IEEE NPSS Conference, 2007

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Advances in architectures and tools for FPGAs and their impact on the design of complex systems for particle physics

William Plishker, Amin Farmahini-farahani

2009

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PHENIX Level-1 Trigger systems for RHIC run-3

Steven Skutnik

2002 IEEE Nuclear Science Symposium Conference Record, 2003

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The PHENIX Level-1 trigger system

Athanasios Petridis

1999 IEEE Conference on Real-Time Computer Applications in Nuclear Particle and Plasma Physics. 11th IEEE NPSS Real Time Conference. Conference Record (Cat. No.99EX295)

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A High-End Reconfigurable Computation Platform for Nuclear and Particle Physics Experiments

Shuo Yang

Computing in Science & Engineering, 2000

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GPUs for the realtime low-level trigger of the NA62 experiment at CERN

Piero Vicini

2015

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TEL62: an integrated trigger and data acquisition board

Elena Pedreschi

2011 IEEE Nuclear Science Symposium Conference Record, 2011

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Thierry Romanteau

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018), 2019

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Stefano Veneziano

2001

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NaNet: a Reconfigurable PCIe Network Interface Card Architecture for Real-time Distributed Heterogeneous Stream Processing in the NA62 Low Level Trigger

Piero Vicini

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)

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Real-time heterogeneous stream processing with NaNet in the NA62 experiment

Alessandro Lonardo

Journal of Physics: Conference Series, 2018

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The electron/photon and tau/hadron Cluster Processor for the ATLAS First-Level Trigger-a Flexible Test System V. Perera, I. Brawn, J. Edwards, CNP Gee, …

Sten Hellman

Proceedings of the fifth …, 1999

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The electron/photon and tau/hadron Cluster Processor for the ATLAS First-Level Trigger - a Flexible Test System

ANWAR SHAH

1999

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Performance of the NA62 trigger system

Adolfo Fucci

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Ultrahigh Energy Heavy Ion Test Beam on Xilinx Kintex-7 SRAM-Based FPGA

David Codinachs

IEEE Transactions on Nuclear Science, 2019

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Thiago Fernandez

2019

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Use of the ESOP fast processor in the trigger logic of the CERN experiment NA-11

Bartlomiej Kisielewski

Computer Physics Communications, 1981

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A high-resolution TDC-based board for a fully digital Trigger and Data AcQuisition system in the NA62 experiment at CERN

MARCO STANISLAO SOZZI

2014 19th IEEE-NPSS Real Time Conference, 2014

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The Los Alamos Accelerator Code Group

Frank Krawczyk

Proceedings Particle Accelerator Conference, 1995

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CAPTAN: A hardware architecture for integrated data acquisition, control, and analysis for detector development

Marcos Turqueti

2008 IEEE Nuclear Science Symposium Conference Record, 2008

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Graphics Processors in HEP Low-Level Trigger Systems

Piero Vicini

EPJ Web of Conferences, 2016

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