Comparison of LER Induced Mismatch in NWFET and NSFET for 5-nm CMOS (original) (raw)
Related papers
Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability
IEEE Transactions on Electron Devices, 2000
We present a model for estimating the impact of gate line edge roughness (LER) on the performance of doublegate (DG) FinFET devices. Thirteen-nanometer-gate-length DG FinFETs are investigated using a framework that links device performance to commonly used LER descriptors, namely, correlation length (ξ), rms amplitude or standard deviation (σ) of the line edge from its mean value, and roughness exponent (α). Our approach provides physical insight into how LER impacts FinFET performance. In addition, our modeling approach is more efficient than Monte Carlo TCAD simulations and provides comparable results with appropriately selected input parameters. The FinFET device architecture is found to be robust to gate LER effects. Furthermore, a spacer-defined gate electrode (versus a resist-defined gate electrode) provides for reduced variability in performance, indicating that the gate length mismatch has more impact than lateral offset between the front and the back gates.
Full 3D Statistical Simulation of Line Edge Roughness in sub-100nm MOSFETs
Line Edge Roughness (LER), caused by tolerances inherent to materials and tools used in lithography processes, is not a new phenomenon. Yet, the imperfections caused by LER have caused little worry over the years since the critical dimensions of MOSFETs were almost two orders of magnitude larger than the roughness. However, as the aggressive scaling of Si-MOSFETs continues to the sub-100 nm regime, LER does not diminish but constitutes an increasingly larger fraction of the gate length. Indeed, at the end of the SIA Roadmap [1], MOSFETs with gate length as small as 20 nm are anticipated, making LER one of the critical problems for ULSI, where millions of devices must operate in very strict margins on a single chip.
Modeling line edge roughness effects in sub 100 nanometer gate length devices
2000
A fast method to estimate the effects of line edge roughness is proposed. This method is based upon the use of multiple 2D device “slices” sandwiched together to form a MOS transistor of a given width. This method was verified to yield an accurate representation of rough edge MOS transistors through comparisons to full three dimensional simulations. A subsequent statistical study shows how the variation in line edge roughness affects the values and variances of several key device parameters
Journal of Low Power Electronics and Applications, 2015
In this paper, we analyze the variability of III-V homojunction tunnel FET (TFET) and FinFET devices and 32-bit carry-lookahead adder (CLA) circuit operating in near-threshold region. The impacts of the most severe intrinsic device variations including work function variation (WFV) and fin line-edge roughness (fin LER) on TFET and FinFET device Ion, Ioff, Cg, 32-bit CLA delay and power-delay product (PDP) are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations and HSPICE simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. The results indicate that WFV and fin LER have different impacts on device Ion and Ioff. Besides, at low operating voltage (<0.3 V), the CLA circuit delay and power-delay product (PDP) of TFET are significantly better than FinFET due to its better Ion and Cg,ave and their smaller variability. However, the leakage power of TFET CLA is larger than FinFET CLA due to the worse Ioff variability of TFET devices.
A novel approach to simulate Fin-width Line Edge Roughness effect of FinFET performance
2010
This paper developed a full three-dimensional (3-D) statistical simulation approach to investigate Fin-width Line Edge Roughness (LER) effect on the FinFETs performance. The line edge roughness is introduced by Matlab program, and then the intrinsic parameter fluctuations at fixed LER parameters are studied in carefully designed simulation experiments. The result shows that Fin-width LER causes a dramatic shift and fluctuations in threshold voltage. The simulation results also imply that the velocity saturation effect may come into effect even under low drain voltage due to LER effect.
Prediction Model for Random Variation in FinFET Induced by Line-Edge-Roughness (LER)
Electronics
As the physical size of MOSFET has been aggressively scaled-down, the impact of process-induced random variation (RV) should be considered as one of the device design considerations of MOSFET. In this work, an artificial neural network (ANN) model is developed to investigate the effect of line-edge roughness (LER)-induced random variation on the input/output transfer characteristics (e.g., off-state leakage current (Ioff), subthreshold slope (SS), saturation drain current (Id,sat), linear drain current (Id,lin), saturation threshold voltage (Vth,sat), and linear threshold voltage (Vth,lin)) of 5 nm FinFET. Hence, the prediction model was divided into two phases, i.e., “Predict Vth” and “Model Vth”. In the former, LER profiles were only used as training input features, and two threshold voltages (i.e., Vth,sat and Vth,lin) were target variables. In the latter, however, LER profiles and the two threshold voltages were used as training input features. The final prediction was then made...
IEEE Transactions on Electron Devices, 2013
Investigations on device variability for three different emerging field-effect transistor (FET) technologies are performed to determine the statistical dependence or independence of line edge roughness (LER) and random dopant fluctuation (RDF) variability mechanisms. The device candidates include standard inversion-mode (IM) FinFETs, junctionless (JL) FinFETs, and tunnel FETs (TFETs) designed for sub-32-nm generations. Using technology computer-aided design simulations, extracted standard deviations in linear and saturation threshold voltages (V T,lin and V T,sat), ON-state current (I ON), OFF-state current (I OFF), subthreshold swing (SS), and draininduced barrier lowering (DIBL) are compared for the cases: 1) when LER and RDF are separately modeled during device simulations and assumed to combine in an uncorrelated fashion, and 2) when LER and RDF are simultaneously modeled in device simulations and no assumption is made about their interaction. After performing the comparisons for each FET technology, we find that LER and RDF cannot be considered independent for IM-FinFETs and TFETs, but can be for JL-FinFETs. The different outcomes are related to local versus distributed variability dependencies in each transistor type. Our conclusions reinforce the need for more comprehensive treatment of variability effects to provide accurate estimations of expected device variability in junction-based FETs.
IEEE Transactions on Electron Devices, 2000
We study the effect of surface roughness (SR) at the Si/SiO 2 interfaces on transport properties of quasi 1-D and 2-D silicon nanodevices by comparing the electrical performances of nanowire (NW) and double-gate (DG) field-effect transistors. We address a full-quantum analysis based on the 3-D self-consistent solution of the Poisson-Schrödinger equation within the coupled mode-space nonequilibrium Green function (NEGF) formalism. The influence of SR scattering is also compared with phonon (PH) scattering addressed in the self-consistent Born approximation. We analyze transfer characteristics, current spectra, density of states, and low-field mobility of devices with different lateral size, showing that the dimensionality of the quasi 1-D and 2-D structures induces significant differences only for thin silicon thicknesses. Thin NWs are found more sensitive to the SR-induced variability of the threshold voltage with respect to the DG planar transistors.
Journal of Nanoscience and Nanotechnology, 2017
In this paper, characteristics of line edge roughness (LER) and process variation effect (PVE) were investigated for a three stacked gate-all-around (GAA) nanowire (NW) field effect transistor (FET) through 3-D technology computer-aided design (TCAD) simulations. The stacked device has robust immunity for GAA LER as well as high driving current in comparison with single NW FET. On the other hand, the stacked device has PVE, which causes the difference of channel thickness on each stack. Particularly, the channel of the bottom region has larger channel radius than that of the other stacks. As the disparity of each stack becomes larger, the driving currents are concentrated on the bottom channel, which leads to high stress such as hot carrier degradation on the bottom channel.
Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs
Simulation of Semiconductor Processes and Devices 2001, 2001
We present a full-3D statistical analysis of line edge roughness (LER) in sub-0.1 µm MOSFETs. The modelling approach for line edges and the parameters used in the analysis take into account the statistical nature of the roughness. The results indicate that intrinsic fluctuations in MOSFETs due to LER become comparable in size to random dopant effects and can seriously inhibit scaling below 50 nm.